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參數(shù)資料
| 型號(hào)： | MC68HC05BD3P |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 60/112頁 |
| 文件大小： | 864K |
| 代理商： | MC68HC05BD3P |
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MC68HC05BD3
MOTOROLA
7-5
M-BUS SERIAL INTERFACE
7
7.2.7
Clock Synchronization
Since wire-AND logic is performed on the SCL line, a high to low transition on SCL line will affect
the devices connected to the bus. The devices start counting their low period and once a device's
clock has gone low, it will hold the SCL line low until the clock high state is reached. However, the
change of low to high in this device clock may not change the state of the SCL line, if another
device clock is still in its low period. Therefore synchronized clock SCL will be held low by the
device which releases SCL to a logic high in the last place. Devices with shorter low periods enter
a high wait state during this time (see Figure 7-3). When all devices concerned have counted off
their low period, the synchronized clock SCL line will be released and go high. All of them will start
counting their high periods. The rst device to complete its high period will again pull the SCL line
low.
7.2.8
Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave device
may hold the SCL low after completion of one byte transfer (9 bits). In such case, it will halt the
bus clock and force the master clock in a wait state until the slave releases the SCL line.
7.3
M-Bus Registers
There are ve registers used in the M-Bus interface, these are discussed in the following
paragraphs.
Figure 7-3 Clock Synchronization
SCL1
SCL2
SCL
Internal counter reset
WAIT
Start counting high period
TPG
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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