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參數(shù)資料
| 型號： | MC68HC05CJ4FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 41/114頁 |
| 文件大?。?/td> | 4047K |
| 代理商： | MC68HC05CJ4FB |
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GENERAL RELEASE SPECIFICATION
MODES OF OPERATION
MC68HC(7)05CJ4
6-2
Rev. 2.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Figure 6-1. MC68HC(7)05CJ4 Mode Entry Diagram
6.3 Single-Chip Mode (SCM)
In this mode, all address and data bus activity occurs within the MCU so no
external pins are required for these functions. The single-chip mode allows the
maximum number of I/O pins for on-chip peripheral functions, port A through
port D.
6.4 Self-Check/Bootstrap Mode
In this mode, the reset vector is fetched from a 240-byte internal self-check
(bootstrap for MC68HC705CJ4) ROM at $1F00:$1FEF. The self-check ROM
contains a self-check program to test the functions of internal modules. The
bootstrap ROM contains a small program which reads a program into the internal
RAM and then passes control to that program at location $0020, or executes
EPROM programming sequence and dumps EPROM contents.
Since these modes are not normal user modes, all of the privileged control bits are
accessible. This allows the self-check/bootstrap mode to be used for self testing
the device.
6.5 Low-Power Modes
The following sub-sections describe the low-power modes. Figure 6-2 provides a
timing diagram of the stop recovery mode and Figure 6-3 a flowchart for the stop
and wait modes.
RESET
IRQ1
PB6:7
SINGLE-CHIP
VTST
H
L
H
L
H
L
* VTST = 1.8 x VDD
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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