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| 型號： | MC68HC05CJ4FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 77/114頁 |
| 文件大?。?/td> | 4047K |
| 代理商： | MC68HC05CJ4FB |
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GENERAL RELEASE SPECIFICATION
SERIAL PERIPHERAL INTERFACE
MC68HC(7)05CJ4
9-8
Rev. 2.1
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9.3.3 SPI Data Register (SPDR)
Read: anytime (normally only after SPIF flag set)
Write: anytime (see WCOL write collision flag)
Reset: does not affect this register
This 8-bit register is both the input and output register for SPI data. In the SPI
system the 8-bit data register in the master and the 8-bit data register in the slave
are linked by the MOSI and MISO wires to form a distributed 16-bit register. When
a data transfer operation is performed, this 16-bit register is serially shifted eight bit
positions by the SCK1 clock from the master so the data is effectively exchanged
between the master and the slave. Note that some slave devices are very simple
and either accept data from the master without returning data to the master or pass
data to the master without requiring data from the master.
When writing the SPDR, the data is written directly into the shift register and always
shifted out in the same direction. To affect a change in the direction of data transfer,
the data is loaded into the shift register in reverse order. For this reason, the DOD
bit must be written before data is loaded into the shift register
When reading the SPDR, a read data buffer is actually accessed. This buffer
contains the last data byte received by the SPI, and is updated during the cycle that
SPIF is set (reception complete).
Bit 7
654321
Bit 0
$000D
SPSR
Read:
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
Write:
Reset:
Unaffected by Reset
Figure 9-4. SPI Control Register
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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