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參數(shù)資料
| 型號： | MC68HC05CJ4FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 98/114頁 |
| 文件大小： | 4047K |
| 代理商： | MC68HC05CJ4FB |
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GENERAL RELEASE SPECIFICATION
TIMER 1
MC68HC(7)05CJ4
11-8
Rev. 2.1
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A problem can occur when using the timer overflow function and reading the
free-running counter at random times to measure an elapsed time. Without
incorporating the proper precautions into software, the timer overflow flag could
unintentionally be cleared if:
1. The timer status register is read or written when TOF is set, and
2. The LSB of the free-running counter is read but not for the purpose of
servicing the flag.
The counter alternate register at address $1A and $1B contains the same value as
the free-running counter (at address $18 and $19); therefore, this alternate register
can be read at anytime without affecting the timer overflow flag in the timer status
register.
11.7 Timer 1 During Wait Mode
The CPU clock halts during the wait mode, but the timer remains active. If
interrupts are enabled, a timer interrupt will cause the processor to exit the wait
mode.
11.8 Timer 1 During Stop Mode
In the stop mode, the timer stops counting and holds the last count value if STOP
is exited by an interrupt. If reset is used, the counter is forced to $FFFC. During
stop, if at least one valid input capture edge occurs at the TCAP pin, the input
capture detect circuit is armed. This does not set any timer flags nor wake up the
MCU, but when the MCU does wake up, there is an active input capture flag and
data from the first valid edge that occurred during the stop mode. If reset is used
to exit stop mode, then no input capture flag or data remains, even if a valid input
capture edge occurred.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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