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| 型號： | MC68HC05CJ4FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 94/114頁 |
| 文件大?。?/td> | 4047K |
| 代理商： | MC68HC05CJ4FB |
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GENERAL RELEASE SPECIFICATION
TIMER 1
MC68HC(7)05CJ4
11-4
Rev. 2.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Figure 11-2. Timer 1 Output Compare Operation
Because neither the output compare flag (OCF bit) or output compare register is
affected by reset, care must be exercised initializing the output compare function
with software. The following procedure is recommended:
Write to the high byte of the output compare register to inhibit further compares
until the low byte is written.
Read the timer status register to clear the OCF bit if it is already set.
Write to the low byte of the output compare register to enable the output compare
function.
The purpose of this procedure is to prevent the OCF bit from being set between the
writes to the high and low halves of the 16-bit output compare register. A software
example follows:
B7
16
STA
OCRH
inhibit output compare
B6
13
LDA
T1SR
clear OCF bit if set
BF
17
STX
OCRL
ready for next compare
11.4 Input Capture Register
Two 8-bit registers, which make up the 16-bit input capture register, are read-only
and are used to latch the value of the free-running counter after the corresponding
input capture edge detector senses a defined transition. The level transition which
triggers the counter transfer is defined by the corresponding input edge bit (IEDG).
Reset does not affect the contents of the input capture register.
The result obtained by an input capture will be one more than the value of the
free-running counter on the rising edge of the internal bus clock preceding the
external transition. This delay is required for internal synchronization. Resolution is
one count of the free-running counter, which is four internal bus clock cycles.
The free-running counter contents are transferred to the input capture register on
each proper signal transition regardless of whether the input capture flag (ICF) is
OCIE
INT
OCF
16-BIT COMPARATOR
COUNTER HIGH BYTE
COUNTER LOW BYTE
15
8
7
0
15
8
7
0
16-BIT OUTPUT COMPARE 1 REGISTER
PIN CONTROL
LOGIC
TCMP
PIN
OLVL
=?
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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