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| 型號： | MC68HC05CJ4FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 78/114頁 |
| 文件大?。?/td> | 4047K |
| 代理商： | MC68HC05CJ4FB |
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GENERAL RELEASE SPECIFICATION
SLAVE-ONLY M-BUS
Rev. 2.1
10-1
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SECTION 10
SLAVE-ONLY M-BUS
10.1 Introduction
Freescale bus (M-bus for short) is a two-wire bidirectional bus which provides a
simple, efficient method of providing data exchange between devices. It is fully
compatible to the I2c bus standard.This device will contain a reduced version of the
M-bus supporting only the slave mode. Slave address recognition is provided in
hardware with the value of the address being initialized by the user. Also included
is automatic generation of the acknowledge for both address and data, general call
address recognition, and automatic clock stretching.
10.2 Operation of SOMB and Ninth-Bit Detector
The SOMB consists of an 8-bit synchronous shift register, a start/stop detect
circuit, a ninth-bit detector, and acknowledge detector. The Serial DAta line (SDA)
and Serial CLock line (SCL) share external connections with two bits of port D.
These bits are not enabled during serial operation. The operation of the SOMB is
best described in phases as shown in the following sub-sections.
10.2.1 After Reset
After the MCU has completed the reset operation, the SOMB is in the
following condition:
SME = 0. The SOMB is disabled and the parallel I/O are enabled.
By definition, SMIE and SMF also = 0.
Data = ?. The contents of the data register is unknown.
To enable the SOMB, set SME and SMIE. This will allow the CPU to be interrupted
upon reception of the slave address and/or serial data.
10.2.2 First Reception
The first reception must be proceeded by the start condition. By definition, the first
reception consists of the slave address (seven bits) and the R/W bit. When the start
condition is detected, the SCL input is enabled and the slave's address is
transferred from the address register into the shift register. On the first clock pulse
the external serial data (MSB of the master address) is shifted into the shift register,
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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