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| 型號： | MC68HC05CJ4FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 85/114頁 |
| 文件大?。?/td> | 4047K |
| 代理商： | MC68HC05CJ4FB |
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GENERAL RELEASE SPECIFICATION
SLAVE-ONLY M-BUS
Rev. 2.1
10-7
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10.5 M-Bus Address/Data Register (MBADR)
First access:
Figure 10-3. M-Bus Address/Data Register
Subsequent accesses:
Figure 10-4. M-Bus Data Address/Register
This register has a dual purpose. The initial write to the MBADR must be the slave
address. This data is actually stored in a buffer for use after a start condition has
been detected. Subsequent writes go directly into serial shift register for
transmission. The data register is not buffered. This means that reading or writing
the MBADR during a transmission can corrupt the data. Reads of the MBADR
always give back the contents of the shift register, which is undefined until after the
first reception.
The address match is done for bits 1:7. Bit 0 is not compared and contains the R/W
bit when read.
Reset has no effect on the data register, but the address buffer is cleared to $00
and MUST be initialized by the user.
Bit 7
654321
Bit 0
$001C
MBADR
Read:
MSR7
MSR6
MSR5
MSR4
MSR3
MSR2
MSR1
MSR0
Write:
MBA7
MBA6
MBA5
MBA4
MBA3
MBA2
MBA1
MBR/W
Reset:
UUUUUUUU
U = Unaffected
Bit 7
654321
Bit 0
$001C
MBADR
Read:
MSR7
MSR6
MSR5
MSR4
MSR3
MSR2
MSR1
MSR0
Write:
MBD7
MBD6
MBD5
MBD4
MBD3
MBD2
MBD1
MBD0
Reset:
UUUUUUUU
U = Unaffected
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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