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參數(shù)資料
| 型號： | MC68HC05E0FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 42/96頁 |
| 文件大?。?/td> | 890K |
| 代理商： | MC68HC05E0FN |
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5
MC68HC05E0
MOTOROLA
5-1
MEMORY AND ADDRESSING
5
MEMORY AND ADDRESSING
5.1
Memory Map
As shown in Figure 5-1, the MC68HC05E0 is capable of addressing a full 65536 bytes of memory
and I/O using a non-multiplexed bus. The address space is divided into internal memory space
and external memory space as shown in the memory map. The internal memory space is located
within the rst 512 bytes of memory (pages 0 and 1) and contains the I/O port data and data
registers, all the timer, Serial Interface and wake-up control and data registers, and 480 bytes of
RAM. Program writes to on-chip locations are repeated on the external bus enabling off-chip
memory to duplicate the contents of on-chip memory. Program reads from on-chip locations also
appear on the external bus, but the CPU accepts data only from the addressed on-chip locations,
and ignores data appearing on the input bus.
5.2
RAM
480 bytes of on-chip static RAM are located from $0020 to $01FF. The processor stack starts at
$00FF and is limited to 64 bytes ($00C0 to $00FF). When the stack overows it wraps round from
$00C0 to $00FF, overwriting any existing data.
Note:
Using the stack area for data storage or as temporary work locations requires care to
prevent it from being overwritten due to stacking from an interrupt or subroutine call.
External RAM can be located from $0200 to $1FFF and accessed via the external data and
address buses. PD2 (Port D, bit 2) can be congured to output a chip select signal (CS2) which
can be used to select the external RAM, when an address in this range is present on the address
bus.
47
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