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參數(shù)資料
| 型號： | MC68HC05E0FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 71/96頁 |
| 文件大?。?/td> | 890K |
| 代理商： | MC68HC05E0FN |
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8
MC68HC05E0
MOTOROLA
8-7
SERIAL INTERFACE
A typical I2C-bus transaction starts with the MC68HC05E0 generating a START condition (SDA
pulled low while SCL high). The MC68HC05E0 will then send a stream of 8 bits. The SCL line is
pulsed to provide a clock waveform while data is sent. The rst 7 bits of the byte specify the
address of a slave peripheral, and the 8th bit species the direction of data between the slave and
the micro - a “0” indicates write to slave, a “1” indicates read from slave. A 9th clock pulse is
generated during which the addressed slave can indicate acknowledgement to the micro. This is
done by the micro releasing the data line and the slave pulling the data line low. Successive bursts
of 9 clock pulses are generated by the micro to synchronize transfer of data, and the receiver has
the possibility to acknowledge on the 9th pulse. Data transfer is terminated by the micro
generating a STOP condition (SDA goes high while SCL high).
The I2C-bus Interface is congured via the SI Mode Register ($0010)
SIE — Serial Interrupt Enable Bit
This bit masks the interrupt signal generated at the end of each I2C transfer.
1 (set)
–
Interrupts not masked
0 (clear) –
Interrupts masked
Figure 8-3 I2C-bus Data/Clock Relationship
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Port E/SI mode register
$0010
SIE
CPHA
CPOL
WL
BD‘1
BD0
PS1
PS0
0000 0000
SCL
SDA
1
2
3
4
5
6
7
8
9
MSB
LSB
START
STOP
Receiver Acknowledge
– Data changes following falling edge on SCL
– Data stable while SCL high
Transmission of 1 Data Byte (I 2C Bus), with START and STOP
73
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