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參數(shù)資料
| 型號： | MC68HC05E0FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 65/96頁 |
| 文件大小： | 890K |
| 代理商： | MC68HC05E0FN |
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8
MOTOROLA
8-2
MC68HC05E0
SERIAL INTERFACE
The sequence of events for starting a send/receive sequence in either SPI or I2C-bus mode is as
follows:
1) Write to SI Mode register ($0010). The state of bits 0 and 1 select the data
and clock lines, and the protocol (see Table 8-1).
2) If sending data from the MCU to a peripheral, write the data to be sent to the
SI Data register ($000F).
3) Start the send/receive sequence by writing a “1” to the DOIT bit (bit 5 in the
Serial Interface Control/Status Register, the SI S Register, $0011).The SI S
Register also contains control bits to determine the data direction, and
whether STOP/START bits are to be added to the data (I2C-bus only).
The transmission rate in SPI and I2C-bus mode is determined by BD0 and BD1 (bits 2 and 3 in
the SI Mode Register) which control the division ratio applied to the subsystem clock (see
Figure 8-1). The division ratios are listed in Table 8-2. Note that the maximum SI transfer rate =
P02
÷ 6 (i.e. when SC0, SC1, BD0 and BD1 are all set to 1).
Figure 8-1 Serial Port Baud Rate Generation
Table 8-2 BD0, BD1: Serial Port Transfer Rate Selection
BD1
BD0
SI transfer rate
0
fSUB ÷ 48
0
1
fSUB ÷ 24
1
0
fSUB ÷ 12
1
fSUB ÷ 6
0
1
2
3
MUX
÷3
÷2
Sub-system
Clock
BD1
BD0
SPI / I C-Clock
(Baud Rate)
2
68
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