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參數(shù)資料
| 型號： | MC68HC05E0FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 43/96頁 |
| 文件大小： | 890K |
| 代理商： | MC68HC05E0FN |
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5
MOTOROLA
5-2
MC68HC05E0
MEMORY AND ADDRESSING
5.3
ROM
External ROM can be located from $0200 to $FFFF and accessed via the external data and
address buses. (Address lines A0 to A12 are always available; PD5 to PD7 (Port D bits 5 to 7) can
be congured as address lines A13 to A15 to provide addressing above $8000.) Chip select signal
CSROM can be used to select the external ROM, when an address in the range $3000-$FFFF is
present on the address bus.
Note:
Writing a logic zero to bit 2 (XROM) of the Timer Control Register ($000C) causes the
CSROM output to remain permanently low throughout the full memory map
($0000-$FFFF). Clearing XROM also sets the external data bus lines to INPUT only
(See Section 2.9).
5.4
Registers
Internal registers associated with the on-board hardware functions are located from $0000 to
$001F. All internal registers and their contents are shown in Table 5-1.
External I/O (on peripheral devices) can be located from $2000 to $2FFF and accessed via the
external data and address buses. PD3 (Port D, bit 3) can be congured to output a chip select
signal (CS3) which can be used to select the external I/O, when an address in this range is present
on the address bus.
5.5
Vectors
All vectors for reset, hardware interrupts and software interrupt are located at the top of the
memory map, from $FFF4 to $FFFF, as shown in Figure 3-1. Each vector location consists of two
bytes containing the start address (in ROM) of the reset or interrupt routine (see Table 5-2).
5.6
Address Decoding and System Expansion
The address decoder partitions the entire memory space into RAM, ROM, register and interrupt
vector areas. This allows access to external blocks of memory and peripherals as well as to the
on-chip RAM and all the registers supporting the on-chip hardware functions. Address bus and
data bus lines (A0 to A12 and D0 to D7, respectively) and chip select signal CSROM are always
available. In addition, Port D can be congured (via the Port D Mode register) to provide the
following address, control and chip select signals:-
48
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