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參數(shù)資料
| 型號： | MC68HC05E0FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 66/96頁 |
| 文件大?。?/td> | 890K |
| 代理商： | MC68HC05E0FN |
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8
MC68HC05E0
MOTOROLA
8-3
SERIAL INTERFACE
On completion of the transmit/receive sequence internal logic sets the IRQACK ag (bit 4 in the
SI S Register) high, and an interrupt will be generated if the SIE bit (bit 7 in the SI Mode Register)
was set high. In both SPI and I2C-bus mode, when the serial interface is in send mode, the data
on the external data line is sampled 3 times per data bit. The majority value of the sample (the
value found by at least 2 out of 3 of the samples) is compared with the expected state of data. If
they are not the same, the TFF (Transmission failure) ag (bit 5 of the SI S Register) is set. This
indicates that, due perhaps to noise or a hard fault such as a short circuit on the data line, the
transmitted data and the actual data on the line do not match. TFF is a read-only signal. TFF is
set at the end of an SPI/I2C-bus sequence.
8.2
SPI Conguration
The SPI serial interface allows data to be sent or received by the MCU over a single, bidirectional
data line. An accompanying clock signal is also generated by the MCU.
Four different combinations of clock phase/polarity can be generated under the control of CPOL
and CPHA (bits 5 and 6 respectively in the SI Mode Register, $0010). (Refer to Figure 8-2)
The clock and data pins selected by PS0 and PS1 are open-drain. External 4k7 pull-up resistors
should be used. The external data line is hi-Z (pulled high by the external resistor) when the SPI
is idle. The idle state of the clock line depends on the setting of CPOL/CPHA. Refer to Section 9
for more detailed information on SPI timing.
Figure 8-2 SPI Data/Clock Relationship
Idle line or
preceding
transmission
Start
8 Data Bits
Clock
(CPOL=0, CPHA=0)
Clock
(CPOL=0, CPHA=1)
Clock
(CPOL=1, CPHA=0)
Clock
(CPOL=1, CPHA=1)
Stop
Data
0
1
2
3
4
5
6
7
Stop
MSB
LSB
Start
69
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