參數(shù)資料
型號: MC68HC05J5P
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20
封裝: PLASTIC, DIP-20
文件頁數(shù): 20/69頁
文件大?。?/td> 394K
代理商: MC68HC05J5P
December 11, 1996
GENERAL RELEASE SPECIFICATION
MC68HC05J5
INTERRUPTS
MOTOROLA
REV 1.1
4-1
SECTION 4
INTERRUPTS
The CPU can be interrupted in ve different ways:
Non-maskable Software Interrupt Instruction (SWI)
External Asynchronous Interrupt (IRQ)
Optional External Interrupt on PA0-PA3 (mask option)
External Interrupt on PA7
Internal Timer Interrupt
4.1
CPU INTERRUPT PROCESSING
Interrupts cause the processor to save register contents on the stack and to set
the interrupt mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware
interrupts do not cause the current instruction execution to be halted, but are
considered pending until the current instruction is complete.
If interrupts are not masked (I-bit in the CCR is clear) and the corresponding
interrupt enable bit is set the processor will proceed with interrupt processing.
Otherwise, the next instruction is fetched and executed. If an interrupt occurs the
processor completes the current instruction, then stacks the current CPU register
states, sets the I-bit to inhibit further interrupts, and nally checks the pending
hardware interrupts. If more than one interrupt is pending following the stacking
operation, the interrupt with the highest vector location shown in Table 4-1 will be
serviced rst. The SWI is executed the same as any other instruction, regardless
of the I-bit state.
When an interrupt is to be processed the CPU fetches the address of the
appropriate interrupt software service routine from the vector table at locations
$07F8 to $07FF as dened in Table 4-1.
Table 4-1. Vector Address for Interrupts and Reset
N/A
IRQF/IRQF1
TOF
RTIF
Register
N/A
ICSR
TCSR
Flag
Name
Interrupts
Reset
Software
External Interrupt
Timer Overflow
Real Time Interrupt
CPU
Interrupt
RESET
SWI
IRQ
TIMER
Vector Address
$07FE-$07FF
$07FC-$07FD
$07FA-$07FB
$07F8-$07F9
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