參數(shù)資料
型號(hào)： MC68HC05J5P
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20
封裝： PLASTIC, DIP-20
文件頁(yè)數(shù)： 25/69頁(yè)
文件大小： 394K
代理商： MC68HC05J5P
December 11, 1996
GENERAL RELEASE SPECIFICATION
MC68HC05J5
INTERRUPTS
MOTOROLA
REV 1.1
4-5
IRQF1 - PA7 Interrupt Request Flag
Writing to the IRQF1 ag bit will have no effect on it. If the additional setting of
IRQF1 ag bit is not cleared in the IRQ service routine and the IRQE1 enable
bit remains set the CPU will re-enter the IRQ interrupt sequence continuously
until either the IRQF1 ag bit or the IRQE1 enable bit is cleared. The IRQF1
latch is cleared by reset.
1 =
Indicates that an IRQ request triggered by a falling edge on PA7 is
pending.
0 =
Indicates that no IRQ request triggered by a falling edge on PA7 is
pending. The IRQF1 ag bit can ONLY be cleared by writing a logic
one to the IRQR1 acknowledge bit. Doing so before exiting the
service routine will mask out additional occurrences of the IRQF1.
IRQF - IRQ Interrupt Request Flag
Writing to the IRQF ag bit will have no effect on it. If the additional setting of
IRQF ag bit is not cleared in the IRQ service routine and the IRQE enable bit
remains set the CPU will re-enter the IRQ interrupt sequence continuously until
either the IRQF ag bit or the IRQE enable bit is clear. The IRQF latch is
cleared by reset.
1 =
Indicates that an IRQ request is pending.
0 =
Indicates that no IRQ request triggered by pins PA0-3 or IRQ is
pending. The IRQF ag bit is cleared once the IRQ vector is fetched
AND if IRQE1 is also cleared. If IRQE1 is set, then the only way of
clearing IRQF ag is by writing a logic one to IRQR bit. The IRQF
ag bit can be cleared, regardless of the status of the IRQE1 bit, by
writing a logic one to the IRQR acknowledge bit to clear the IRQ
latch and also conditioning the external IRQ sources to be inactive
(if the level sensitive interrupts are enabled via mask option). Doing
so before exiting the service routine will mask out additional
occurrences of the IRQF.
IRQE1 - PA7 Interrupt Enable
The IRQE1 bit enables/disables the IRQF1 ag bit to initiate an IRQ interrupt
sequence.
1 =
Enables IRQF1 interrupt, that is, the IRQF1 ag bit can generate an
interrupt sequence. Execution of the STOP or WAIT instructions will
leave the IRQE1 bit to be UNAFFECTED.
0 =
The IRQF1 ag bit cannot generate an interrupt sequence. Reset
clears the IRQE1 enable bit, thereby disabling PA7 interrupts.
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