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參數(shù)資料
| 型號(hào)： | MC68HC05J5P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 49/69頁 |
| 文件大?。?/td> | 394K |
| 代理商： | MC68HC05J5P |
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December 11, 1996
GENERAL RELEASE SPECIFICATION
MC68HC05J5
MULTI-FUNCTION TIMER
MOTOROLA
REV 1.1
8-5
Figure 8-4. COP Watchdog Timer Location
8.3
OPERATION DURING STOP MODE
The timer system is cleared when going into STOP mode. When STOP is exited
by an external interrupt or an LVR reset or an external RESET, the internal oscilla-
tor will resume, followed by a 4064 internal processor oscillator stabilization delay.
The timer system counter is then cleared and operation resumes. If chosen by a
mask option, the STOP instruction will initiate HALT mode and the effects on the
timer are as described in Section 8.4.
8.4
OPERATION DURING WAIT/HALT MODE
The CPU clock halts during the WAIT/HALT mode, but the timer remains active. If
interrupts are enabled, a timer interrupt or custom periodic interrupt will cause the
processor to exit the WAIT/HALT mode.
7
W
R
6543210
COP
$07F0
COPR
Reading $07F0 returns the contents of Test ROM.
Unimplemented
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