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參數(shù)資料
| 型號： | MC68HC05J5P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 27/69頁 |
| 文件大?。?/td> | 394K |
| 代理商： | MC68HC05J5P |
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December 11, 1996
GENERAL RELEASE SPECIFICATION
MC68HC05J5
RESETS
MOTOROLA
REV 1.1
5-1
SECTION 5
RESETS
The MCU can be reset from ve sources: one external input and four internal
restart conditions.
5.1
EXTERNAL RESET (RESET)
The RESET pin is the only external source of a reset. This pin is connected to a
Schmitt trigger input gate to provide an upper and lower threshold voltage sepa-
rated by a minimum amount of hysteresis. This external reset occurs whenever
the RESET pin is pulled below the lower threshold and remains in reset until the
RESET pin rises above the upper threshold. This active low input will generate the
RST signal and reset the CPU and peripherals. This pin is also an output pin
whenever the LVR triggers an internal reset. Termination of the external RESET
input or the internal COP Watchdog reset or LVR are the only reset sources that
can alter the operating mode of the MCU.
5.2
INTERNAL RESETS
The four internally generated resets are the initial power-on reset function, the
COP Watchdog Timer reset, the illegal address detector reset and the low voltage
reset (LVR). Termination of the external RESET input or the internal COP Watch-
dog Timer or LVR are the only reset sources that can alter the operating mode of
the MCU. The other internal resets will not have any effect on the mode of opera-
tion when their reset state ends.
5.2.1 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator to stabi-
lize. The POR is strictly for power turn-on conditions and is not able to detect a
drop in the power supply voltage (brown-out). There is an oscillator stabilization
delay of 4064 internal processor bus clock cycles (PH2) after the oscillator
becomes active.
The POR will generate the RST signal which will reset the CPU. If any other reset
function is active at the end of this 4064 cycle delay, the RST signal will remain in
the reset condition until the other reset condition(s) end.
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