3V Control Timing
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor
141
16.9 3V Control Timing
LVI reset voltage
V
LVR3
2.0
2.4
2.69
V
1. V
DD
= 2.7 to 3.3 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25
°
C only.
3. Run (operating) I
DD
measured using external square wave clock source (f
OP
= 2MHz). All inputs 0.2V from rail. No dc
loads. Less than 100 pF on all outputs. C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run I
DD
. Measured with all modules enabled.
4. Wait I
DD
measured using external square wave clock source (f
OP
= 2MHz). All inputs 0.2V from rail. No dc loads. Less
than 100 pF on all outputs. C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait I
DD
.
5. Stop I
DD
measured with OSC1 grounded; no port pins sourcing current. LVI is disabled.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum V
DD
is not reached before the internal POR reset is released, RST must be driven low externally until minimum
V
DD
is reached.
8. R
PU1
and R
PU2
are measured at V
DD
= 5.0V.
Table 16-8. Control Timing (3V)
Characteristic
(1)
1. V
DD
= 2.7 to 3.3 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
; timing shown with respect to 20% V
DD
and 70% V
DD
, unless otherwise
noted.
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this infor-
mation.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
Symbol
Min
Max
Unit
Internal operating frequency
(2)
f
OP
—
4
MHz
RST input pulse width low
(3)
t
IRL
1.5
—
μ
s
Table 16-7. DC Electrical Characteristics (3V) (Continued)
Characteristic
(1)
Symbol
Min
Typ
(2)
Max
Unit