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| 型號： | MC68HC705CJ4FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 52/114頁 |
| 文件大?。?/td> | 4047K |
| 代理商： | MC68HC705CJ4FB |
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GENERAL RELEASE SPECIFICATION
SERIAL COMMUNICATIONS INTERFACE
Rev. 2.1
8-5
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3. Ignore the sample at RT2 and sample RXD at RT3. Call this the first test
sample.
4. Ignore the sample at RT4 and sample RXD at RT5. Call this the second test
sample. If test samples at RT3 and RT5 were both high, assume that the low
detected at RT1 was noise and go back to step 1 else continue.
5. Ignore the sample at RT6 and sample RXD at RT7. Call this the third test
sample. If any two of the test samples at RT3, RT5, or RT7 were high
assume that the low detected at RT1 was noise and go back to step 1 else
continue.
6. A valid start bit has been found and synchronization has been achieved.
From this point on until the end of the frame the RT clock will increment to
RT16 and start over at RT1 where RT1 is considered to be the beginning of
a bit time and RT16 is considered to be the end of a bit time.
NOTE
Any one-to-zero transition will re-synchronize the RT clock and may
shift the assumed location of RT1.
Upon detection of a valid start bit, synchronization has been established and
locked to the internal 16 times baud rate clock. The incoming data is no longer
considered asynchronous until after reception of the stop bit, at which time a new
asynchronous search for a start bit is initiated.
During each bit time of the frame, including the start and stop bit times, three logic
sense samples are taken at RT8, RT9, and RT10. The logic sense of the bit time
is taken to be the sense of the majority of these three samples (except the start bit,
which is assumed to be logic sense zero regardless of the RT8 – RT10 samples).
Note that during the start bit time, samples were also taken at RT1, RT3, RT5, and
RT7 and the samples taken at RT8, RT9, and RT10 during the start bit time are
only used for possible setting of a working “noise flag”. There is a working “noise
flag” associated with each received frame which implies whether or not the
information in the frame is likely to be in error. If the noise flag is clear, it implies
good information, and, if this flag is set, it implies that the data may (but probably
does not) contain errors. At the beginning of a frame, the working noise flag starts
out at zero. If any of the samples taken at RT3, RT5, or RT7 during the start bit
search was a high, the working noise flag will be set. Also, if the samples taken at
RT8, RT9, and RT10 during any one bit time (including the start bit, all data bits,
optional ninth bit, and stop bit) do not all three agree, the working noise flag will
be set.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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