- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69026 > MC68HC705CJ4FB (FREESCALE SEMICONDUCTOR INC) 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP44 PDF資料下載
參數(shù)資料
| 型號(hào)： | MC68HC705CJ4FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 59/114頁(yè) |
| 文件大小： | 4047K |
| 代理商： | MC68HC705CJ4FB |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)當(dāng)前第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)
GENERAL RELEASE SPECIFICATION
SERIAL COMMUNICATIONS INTERFACE
MC68HC(7)05CJ4
8-12
Rev. 2.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
8.3.3 Idle Line Detect
The receive logic hardware includes the ability to detect an idle line. This can be
useful in a system to indicate when one message was finished and another was
about to be started. An idle line is defined as a minimum of 10 (11 if nine data bit
format is selected) bit times of continuous logic ones on the RXD line. During a
normal message, there is no idle time between frames, so even if all information
bits in a frame were logic ones the start bits would ensure that at least one logic
zero bit time occurred for each frame and IDLE would not get set.
When the RXD line goes idle for the minimum required time, the IDLE status bit in
SCSR gets set. If the Idle Line Interrupt Enable (ILIE) bit in the SCCR1 register is
set then a hardware interrupt sequence also will be requested when IDLE gets set.
The IDLE status bit is cleared by reading the SCSR register (with IDLE set)
followed by reading the RDR register. IDLE will not be set again until after at least
one character is received. This prevents an RXD line that remains idle for a long
period of time from causing several interrupts.
8.3.4 Receiver Wakeup
The receiver logic hardware also supports a receiver wake-up function intended for
systems having more than one receiver. With this function, the transmitting device
directs messages to an individual receiver or group of receivers by passing
addressing information as the initial byte(s) of each message. Receivers not
addressed invoke the receiver wake up function which puts these receivers in a
dormant state for the remainder of the unwanted message. This eliminates any
further software overhead to service the remaining characters of the unwanted
message and thus improves performance.
The receiver is placed in wake-up mode by writing a one to the receiver wake-up
(RWU) bit in the SCCR2 register. While RWU is set, all of the receive status flags
(RDRF, IDLE, OR, NF, and FE) are inhibited (cannot be set). Note that
specification of receiver wake-up mode inhibits the use of the idle line detect
function. Although RWU may be cleared by a write to SCCR, it is normally left alone
by software and gets cleared automatically by hardware with one of the two
methods explained in the following paragraphs.
The SCI offers a choice of two methods for waking up receivers from the dormant
state. The first method is called idle line wake up. The second method is called
address mark wake up and operates by using the MSB to differentiate between
address information (MSB set) and data information (MSB clear). The WAKE
control bit in the SCCR1 control register is used to select which method of
automatic hardware wake up is to be used. If the WAKE bit is clear, Idle Line wake
up is specified and if WAKE is set to one, address mark wake up is selected.
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC05E0FN | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQCC68 |
| MC68HC05E5P | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| MC68HC05E5DW | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC05J1ACP | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20 |
| MC68HSC05J1ADW | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC705E6CDW | 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
| MC68HC705G1B | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68HC705J1A | 制造商:Freescale Semiconductor 功能描述: |
| MC68HC705J1ACDW | 功能描述:IC MCU 4MHZ 1.2K OTP 20-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲(chǔ)器容量:64KB（64K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND |
| MC68HC705J1ACP | 功能描述:IC MCU 4MHZ 1.2K OTP 20-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲(chǔ)器容量:64KB（64K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。