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| 型號： | MC68HC705CJ4FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 70/114頁 |
| 文件大?。?/td> | 4047K |
| 代理商： | MC68HC705CJ4FB |
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GENERAL RELEASE SPECIFICATION
SERIAL PERIPHERAL INTERFACE
MC68HC(7)05CJ4
9-2
Rev. 2.1
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9.2.2 Serial Data In (MOSI)
In slave mode, MOSI is the signal used to receive data from some master device.
Figure 9-2 shows the serial clock and data timing relationship.
It should be noted that when a master device transmits data to a second device via
the MOSI line, the slave device (if it has the capability) will respond by sending data
into the MISO pin of the master device. This implies full duplex transmission with
both data out and data in synchronized to the same clock signal which is provided
by the master. Moreover, the SAME shift register is used for data out and data in.
Thus, the byte transmitted is replaced by the byte received, removing the need for
separate status bits for XMIT EMPTY and REC FULL. A single status bit, SPIF, is
used to signify I/O operation complete.
In the master mode, as noted above, the functions of MOSI and MISO are
inverted. The MOSI pin becomes the data output pin when the device is in the
master mode. When a transfer of data is not taking place with a slave device the
master drives the MOSI line high. The master always allows the data onto the
MOSI pin a half-cycle before the clock edge (SCK1) needed for the slave to latch
the data internally.
9.2.3 Serial Clock In/Out (SCK1)
In slave mode, the serial clock is used to move data both in and out of the device
through its MOSI and MISO pins. The master and slave devices are capable of
exchanging a byte of information during a sequence of eight clock pulses if wired
to do so. In the slave mode, the SCK1 pin becomes an input being sent from the
master device for the external clock. In this case SCK1 is asynchronous to the
slave device’s phase 1-2 clocks and read/write control, therefore synchronization
must take place prior to transmission and after reception. This must be done on the
byte level. The type of clock and its relationship with the data is controlled by bits
CPOL and CPHA. Reference Figure 9-2. The clock rate control bits SPR1 and
SPR0 have no function while the part is in the slave mode.
In master mode, the clock is generated within the master device by a circuit driven
from the bus clock. The clock rate is selected by bits (SPR1, SPR0) in the control
register. The SCK1 pin on the master device becomes a fixed output providing the
system clock to an enabled slave or slaves. The clock is used by the master to latch
incoming slave data on the MISO pin and shift out data to the slave device on the
MOSI pin. The master and slave must be operated in the same timing mode. The
type of clock and its relationship with the data is controlled by bits CPOL and
CPHA. Reference Figure 9-2.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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