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| 型號(hào)： | MC68HC705CJ4FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 79/114頁(yè) |
| 文件大小： | 4047K |
| 代理商： | MC68HC705CJ4FB |
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GENERAL RELEASE SPECIFICATION
SLAVE-ONLY M-BUS
MC68HC(7)05CJ4
10-2
Rev. 2.1
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and the first bit of the slave's address (already in the shifter) is shifted out. These
two address bits are compared and if a match occurs, a counter is incremented. If
a match does not occur, the counter is not incremented. This continues for the
duration of the seven bits of address. After the eighth clock pulse, the shift register
stops shifting. The SMF bit is set after the ninth clock pulse.
10.2.3 After the First Reception
When SMF is set, an interrupt request is generated to the CPU based on the
following conditions:
A START condition was recently detected.
The address match counter equals seven
SMIE is set
If the address match counter is less than seven, this means that the slave is not
being addressed. In that case, the start condition and SMF are cleared and the
SCL input is disabled. The SOMB will ignore all further clock pulses until a
subsequent start condition is detected.
If a start condition was not detected on this transmission, then the address match
counter is ignored and the data is treated as data.
If the address is matched and the start was detected, the acknowledge is
accomplished by forcing the SDA line low (in hardware) and enabling the ninth-bit
detector on the clock line. When the ninth clock pulse is detected on the clock line,
the SDA line is released automatically and the SCL line is forced low to stretch the
clock. When the serial service routine is completed, the user must release the
clock line by writing a '0' to CLKR. This serves as a mechanism for releasing the
clock.
NOTE
The M-bus address/data register (MBADR) now has the received
data and bit zero contains the R/W bit from the master. This should
be checked in software and the T/R bit in the slave should be set
accordingly.
The SOMB is now enabled and prepared to receive further data. It will stay in this
mode until another start condition is detected, at which time this process will begin
again.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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| MC68HC705J1ACDW | 功能描述:IC MCU 4MHZ 1.2K OTP 20-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲(chǔ)器容量:64KB（64K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND |
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