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| 型號： | MC68HC705CJ4FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 80/114頁 |
| 文件大?。?/td> | 4047K |
| 代理商： | MC68HC705CJ4FB |
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GENERAL RELEASE SPECIFICATION
SLAVE-ONLY M-BUS
Rev. 2.1
10-3
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10.2.4 Subsequent Receptions
After the first reception, The SMF bit should be cleared by reading the status
register followed by reading or writing the data register, This action clears the serial
interrupt and enables the circuit to receive additional data. Receiving and
acknowledging the data is accomplished in the same way as the first reception.
Stretching the clock is done automatically after every transmission and must be
released by the user each time. If the T/R bit is set, data is transmitted, if it is
cleared data is received. The data register should be serviced before releasing the
clock line in order to avoid data collision.
10.2.5 Acknowledgment
After address detection and data reception, an acknowledge is returned to the
master during the ninth clock pulse. By setting the NOACK bit in the slave M-bus
control register, the acknowledge function will be disabled for the following
transmissions.
During master read, an acknowledge is sent from the receiving master. The status
of the acknowledge could be read from the MACK bit in the slave M-bus status
register during the service routine. This bit is used for detecting the master's
acknowledge and end of transmission. By definition, the end of transmission is
signaled from the master by the absence of the master acknowledge. In this case,
the slave must clear the T/R bit to release the SDA line. If the slave device does
not release the SDA line, the master may not be able to generate the stop
condition.
10.2.6 Stop Condition
The system is capable of detecting the stop condition. This is defined as the rising
edge of the data line while the clock line is high. When this condition is detected,
the system is brought to the state before the start condition.
10.2.7 General Call Address Detect
During address detect cycle (receiving cycle after the start detect), If the resulting
address is $00, a condition of address match is generated. The user must
determine whether this address match is a slave address match or a general call
address match by reading the MBADR (slave MBUS address/data register).
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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