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| 型號： | MC68HLC705KJ1CP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 57/108頁 |
| 文件大?。?/td> | 719K |
| 代理商： | MC68HLC705KJ1CP |
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External Interrupt Module (IRQ)
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
52
Freescale Semiconductor
Figure 5-1. IRQ Module Block Diagram
If edge-sensitive-only triggering is selected, a falling edge on the IRQ/VPP pin latches an external interrupt
request. A subsequent external interrupt request can be latched only after the voltage level on the
IRQ/VPP pin returns to logic 1 and then falls again to logic 0.
The IRQ/VPP pin contains an internal Schmitt trigger as part of its input to improve noise immunity. The
voltage on this pin can affect the mode of operation and should not exceed VDD.
5.3.2 Optional External Interrupts
The inputs for the lower four bits of port A (PA0–PA3) can be connected to the IRQ pin input of the CPU
if enabled by the PIRQ bit in the mask option register. This capability allows keyboard scan applications
where the transitions or levels on the I/O pins will behave the same as the IRQ/VPP pin except for the
inverted phase (logic 1, rising edge). The active state of the IRQ/VPP pin is a logic 0 (falling edge).
The PA0–PA3 pins are selected as a group to function as IRQ interrupts and are enabled by the IRQE bit
in the IRQ status and control register. The PA0–PA3 pins can be positive-edge triggered only or
positive-edge and high-level triggered.
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$000A
IRQ Status and Control
Register (ISCR)
Read:
IRQE
0
IRQF
000
Write:
R
IRQR
Reset:
10
0
0000
= Unimplemented
R
= Reserved
Figure 5-2. IRQ Module I/O Register Summary
PIRQ
LEVEL-SENSITIVE TRIGGER
PA3
PA2
PA1
IRQ
PA0
VDD
(MOR LEVEL BIT)
RESET
IRQ VECTOR FETCH
EXTERNAL
INTERRUPT
REQUEST
(MOR)
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQF
IRQR
IRQE
DQ
CK
IRQ
CLR
LATCH
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