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參數(shù)資料
| 型號： | MC68HLC705KJ1CP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 90/108頁 |
| 文件大?。?/td> | 719K |
| 代理商： | MC68HLC705KJ1CP |
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Multifunction Timer Module
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
82
Freescale Semiconductor
RT1 and RT0 — Real-Time Interrupt Select Bits
These read/write bits select one of four real-time interrupt rates, as shown in Table 9-1. Because the
selected RTI output drives the COP watchdog, changing the real-time interrupt rate also changes the
counting rate of the COP watchdog. Reset sets RT1 and RT0.
NOTE
Changing RT1 and RT0 when a COP timeout is imminent can cause a
real-time interrupt request to be missed or an additional real-time interrupt
request to be generated. To prevent this occurrence, clear the COP timer
before changing RT1 and RT0.
9.5.2 Timer Counter Register
A 15-stage ripple counter is the core of the timer. The value of the first eight stages is readable at any
time from the read-only timer counter register shown in Figure 9-4.
Power-on clears the entire counter chain and the internal clock begins clocking the counter. After 4064
cycles (or 16 cycles if the SOSCD bit in the mask option register is set), the power-on reset circuit is
released, clearing the counter again and allowing the MCU to come out of reset.
A timer overflow function at the eighth counter stage allows a timer interrupt every 1024 internal clock
cycles.
Table 9-1. Real-Time Interrupt Rate Selection
RT1:RT0
RTI Rate
RTI Period
(fOP = 2 MHz)
COP Timeout Period
(–0/+1 RTI Period)
Minimum COP Timeout
Period
(fOP = 2 MHz)
00
fOP ÷ 2
14
8.2 ms
8 x RTI Period
65.5 ms
01
fOP ÷ 2
15
16.4 ms
8 x RTI Period
131.1 ms
10
fOP ÷ 2
16
32.8 ms
8 x RTI Period
262.1 ms
11
fOP ÷ 2
17
65.5 ms
8 x RTI Period
524.3 ms
Address:
$0009
Bit 7
654321
Bit 0
Read:
TCR7
TCR6
TCR5
TCR4
TCR3
TCR2
TCR1
TCR0
Write:
Reset:
00000000
= Unimplemented
Figure 9-4. Timer Counter Register (TCR)
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