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參數(shù)資料
| 型號(hào)： | MC68HLC705KJ1CP |
| 廠(chǎng)商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁(yè)數(shù)： | 60/108頁(yè) |
| 文件大小： | 719K |
| 代理商： | MC68HLC705KJ1CP |
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Timing
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
55
The STOP and WAIT instructions set the IRQE bit so that an external interrupt can bring the MCU out of
these low-power modes. In addition, reset sets the I bit which masks all interrupt sources.
5.5 Timing
Figure 5-5. External Interrupt Timing
Table 5-1. External Interrupt Timing (VDD = 5.0 Vdc)
(1)
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to + 85°C, unless otherwise noted.
Characteristic
Symbol
Min
Max
Unit
IRQ Interrupt Pulse Width Low (Edge-Triggered)
tILIH
1.5
—
tcyc
(2)
2. tcyc = 1/fOP; fOP = fOSC/2.
IRQ Interrupt Pulse Width
(Edge- and Level-Triggered)
tILIH
1.5
Note(3)
3. The minimum tILIL should not be less than the number of interrupt service routine cycles plus 19 tcyc.
tcyc
PA0–PA3 Interrupt Pulse Width High (Edge-Triggered)
tILIL
1.5
—
tcyc
PA0–PA3 Interrupt Pulse Width High (Edge- and Level-Triggered)
tILIH
1.5
Note(3)
tcyc
Table 5-2. External Interrupt Timing (VDD = 3.3 Vdc)
(1)
1. VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to + 85°C, unless otherwise noted.
Characteristic
Symbol
Min
Max
Unit
IRQ Interrupt Pulse Width Low (Edge-Triggered)
tILIH
1.5
—
tcyc
(2)
2. tcyc = 1/fOP; fOP = fOSC/2.
IRQ Interrupt Pulse Width
(Edge- and Level-Triggered)
tILIH
1.5
Note(3)
3. The minimum tILIL should not be less than the number of interrupt service routine cycles plus 19 tcyc.
tcyc
PA0–PA3 Interrupt Pulse Width High (Edge-Triggered)
tILIL
1.5
—
tcyc
PA0–PA3 Interrupt Pulse Width High (Edge- and Level-Triggered)
tILIH
1.5
Note(3)
tcyc
IRQ (INTERNAL)
tILIH
tILIL
tILIH
IRQ/VPP PIN
IRQ1
IRQn
.
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