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參數(shù)資料
| 型號(hào)： | MC68HLC705KJ1CP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁(yè)數(shù)： | 71/108頁(yè) |
| 文件大?。?/td> | 719K |
| 代理商： | MC68HLC705KJ1CP |
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Port A
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
65
Figure 7-4. Port A I/O Circuitry
Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0
disables the output buffer.
When bit DDRAx is a logic 1, reading address $0000 reads the PAx data latch. When bit DDRAx is a logic
0, reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 7-1 summarizes the operation of the port A pins.
7.2.3 Pulldown Register A
Pulldown register A inhibits the pulldown devices on port A pins programmed as inputs.
NOTE
If the SWPDI bit in the mask option register is programmed to logic 1, reset
initializes all port A pins as inputs with disabled pulldown devices.
PDIA[7:0] — Pulldown Inhibit A Bits
PDIA[7:0] disable the port A pulldown devices. Reset clears PDIA[7:0].
1 = Corresponding port A pulldown device disabled
0 = Corresponding port A pulldown device not disabled
Table 7-1. Port A Pin Operation
Data Direction Bit
I/O Pin Mode
Accesses to Data Bit
Read
Write
0
Input, high-impedance
Pin
Latch(1)
1. Writing affects the data register but does not affect input.
1
Output
Latch
Address:
$0010
Bit 7
654321
Bit 0
Read:
Write:
PDIA7
PDIA6
PDIA5
PDIA4
PDIA3
PDIA2
PDIA1
PDIA0
Reset:
00000000
= Unimplemented
Figure 7-5. Pulldown Register A (PDRA)
READ DDRA
WRITE DDRA
RESET
WRITE PORTA
READ PORTA
PAx
INTERN
AL
D
AT
A
B
U
S
DDRAx
PAx
PDRAx
SWPDI
100-
A
PULLDOWN
(PA0–PA3 TO
IRQ MODULE)
WRITE PDRA
10-mA SINK CAPABILITY
(PINS PA4–PA7 ONLY)
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HLC908JK3CP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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