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| 型號： | MC68HLC705KJ1CP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 89/108頁 |
| 文件大小： | 719K |
| 代理商： | MC68HLC705KJ1CP |
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I/O Registers
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
81
9.5 I/O Registers
The following registers control and monitor the timer operation:
Timer status and control register (TSCR)
Timer counter register (TCR)
9.5.1 Timer Status and Control Register
The read/write timer status and control register performs the following functions:
Flags timer interrupts
Enables timer interrupts
Resets timer interrupt flags
Selects real-time interrupt rates
TOF — Timer Overflow Flag
This read-only flag becomes set when the first eight stages of the counter roll over from $FF to $00.
TOF generates a timer overflow interrupt request if TOIE is also set. Clear TOF by writing a logic 1 to
the TOFR bit. Writing to TOF has no effect. Reset clears TOF.
RTIF — Real-Time Interrupt Flag
This read-only flag becomes set when the selected RTI output becomes active. RTIF generates a
real-time interrupt request if RTIE is also set. Clear RTIF by writing a logic 1 to the RTIFR bit. Writing
to RTIF has no effect. Reset clears RTIF.
TOIE — Timer Overflow Interrupt Enable Bit
This read/write bit enables timer overflow interrupts. Reset clears TOIE.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
RTIE — Real-Time Interrupt Enable Bit
This read/write bit enables real-time interrupts. Reset clears RTIE.
1 = Real-time interrupts enabled
0 = Real-time interrupts disabled
TOFR — Timer Overflow Flag Reset Bit
Writing a logic 1 to this write-only bit clears the TOF bit. TOFR always reads as logic 0. Reset clears
TOFR.
RTIFR — Real-Time Interrupt Flag Reset Bit
Writing a logic 1 to this write-only bit clears the RTIF bit. RTIFR always reads as logic 0. Reset clears
RTIFR.
Address:
$0008
Bit 7
654321
Bit 0
Read:
TOF
RTIF
TOIE
RTIE
00
RT1
RT0
Write:
TOFR
RTIFR
Reset:
00000011
= Unimplemented
Figure 9-3. Timer Status and Control Register (TSCR)
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