- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69026 > MC68HSC05P1ADWR2 (MOTOROLA INC) 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO28 PDF資料下載
參數(shù)資料
| 型號： | MC68HSC05P1ADWR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 58/124頁 |
| 文件大?。?/td> | 623K |
| 代理商： | MC68HSC05P1ADWR2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁當(dāng)前第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁
Interrupts
Reset Interrupt Sequence
MC68HC05P1A — Rev. 3.0
General Release Specification
MOTOROLA
Interrupts
39
NON-DISCLOSURE
AGREEMENT
REQUIRED
4.3 Reset Interrupt Sequence
The reset function is not in the strictest sense an interrupt; however, it is
acted upon in a similar manner, as shown in Figure 4-1. A low level input
on the RESET pin or internally generated RST signal causes the
program to vector to its starting address, which is specified by the
contents of memory locations $1FFE and $1FFF. The I bit in the
condition code register is also set. The MCU is configured to a known
state during a reset, as described in Section 5. Resets.
4.4 Software Interrupt (SWI)
The SWI is an executable instruction. It is also a non-maskable interrupt
since it is executed regardless of the state of the I bit in the CCR. As with
any instruction, interrupts pending during the previous instruction will be
serviced before the SWI opcode is fetched. The interrupt service routine
address for the SWI instruction is specified by the contents of memory
locations $1FFC and $1FFD.
4.5 Hardware Interrupts
All hardware interrupts are maskable by the I bit in the CCR. If the I bit
is set, all hardware interrupts (internal and external) are disabled.
Clearing the I bit enables the hardware interrupts. The hardware
interrupts are explained in the following sections.
4.5.1 External Interrupt (IRQ)
The IRQ pin drives an asynchronous interrupt to the CPU. An edge
detector flip-flop is latched on the falling edge of IRQ. If either the output
from the internal edge detector flip-flops or the level on the IRQ pin is
low, a request is synchronized to the CPU to generate the IRQ interrupt.
If the edge-sensitive only mask option is selected, the output of the
internal edge detector flip-flop is sampled and the input level on the IRQ
pin is ignored. The interrupt service routine address is specified by the
contents of memory locations $1FFA and $1FFB. A block diagram of the
IRQ function is shown in Figure 4-2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HCL05P1ADWR2 | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC05P1P | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| MC68HC05P3CDW | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC05P3P | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| MC68HC05P3CP | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HSC705C8ACFB | 制造商:Rochester Electronics LLC 功能描述:8 BIT MCU, 304 BYTES RAM - Bulk |
| MC68HSC705C8ACP | 制造商:Rochester Electronics LLC 功能描述: 制造商:Freescale Semiconductor 功能描述: |
| MC68HSC705C8ACS | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68HSC705J1ACDW | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68HSC705J1ACP | 制造商:Rochester Electronics LLC 功能描述:8 BIT MCU, 64 BYTES RAM - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。