參數(shù)資料
型號(hào): MC68HSC05P1ADWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 75/124頁
文件大?。?/td> 623K
代理商: MC68HSC05P1ADWR2
NON-DISCLOSURE
AGREEMENT
REQUIRED
Operating Modes
General Release Specification
MC68HC05P1A Rev. 3.0
54
Operating Modes
MOTOROLA
6.6 COP Watchdog Timer Considerations
The COP watchdog timer is active in single-chip mode of operation when
selected by mask option. Executing the STOP instruction without
conversion to halt (via mask option) will cause the COP to be disabled.
Therefore, it is recommended that the STOP instruction be modified to
produce halt mode (via mask option) if the COP watchdog timer will be
enabled.
Furthermore, it is recommended that the COP watchdog timer be
disabled for applications that will use the halt or wait modes for time
periods that will exceed the COP timeout period.
COP watchdog timer interactions are summarized in Table 6-2.
Table 6-2. COP Watchdog Timer Recommendations
IF the Following Condition Exists:
THEN the COP Watchdog
Timer Should Be:
STOP Instruction Modes
Wait Period
Halt Mode Selected
via Mask Option
Wait Period Less Than
COP Timeout
Enable or Disable COP
via Mask Option
Halt Mode Selected
via Mask Option
Wait Period More Than
COP Timeout
Disable COP
via Mask Option
Stop Mode Selected
via Mask Option
Any Length Wait Period
Disable COP
via Mask Option
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