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參數(shù)資料
| 型號(hào)： | MC68HSC05P1ADWR2 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 90/124頁(yè) |
| 文件大?。?/td> | 623K |
| 代理商： | MC68HSC05P1ADWR2 |
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NON-DISCLOSURE
AGREEMENT
REQUIRED
16-Bit Timer
General Release Specification
MC68HC05P1A — Rev. 3.0
68
16-Bit Timer
MOTOROLA
8.4 Output Compare
The output compare function may be used to generate an output
waveform and/or as an elapsed time indicator. All of the bits in the output
compare register pair OCRH/OCRL are readable and writable and are
not altered by the 16-bit timer’s control logic. Reset does not affect the
contents of these registers. If the output compare function is not utilized,
its registers may be used for data storage. See Figure 8-2.
The contents of the output compare registers are compared with the
contents of the free-running counter once every four PH2 clock cycles.
If a match is found, the output compare flag bit (OCF) is set and the
output level bit (OLVL) is clocked to the output latch. After each
successful comparison, the values in the output compare registers and
output level bit should be changed to control an output waveform or to
establish a new elapsed timeout. An interrupt also can accompany a
successful output compare if the output compare interrupt enable bit
(OCIE) is set.
OCRH
$0016
Bit 7
654321
Bit 0
Read:
OCRH7
OCRH6
OCRH5
OCRH4
OCRH3
OCRH2
OCRH1
OCRH0
Write:
Reset:
Unaffected by Reset
= Unimplemented
OCRL
$0017
Bit 7
654321
Bit 0
Read:
OCRL7
OCRL6
OCRL5
OCRL4
OCRL3
OCRL2
OCRL1
OCRL0
Write:
Reset:
Unaffected by Reset
= Unimplemented
Figure 8-6. Output Compare Registers (OCRH/OCRL)
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