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參數(shù)資料
| 型號(hào)： | MC68HSC05P1ADWR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 61/124頁(yè) |
| 文件大?。?/td> | 623K |
| 代理商： | MC68HSC05P1ADWR2 |
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Interrupts
Hardware Interrupts
MC68HC05P1A — Rev. 3.0
General Release Specification
MOTOROLA
Interrupts
41
NON-DISCLOSURE
AGREEMENT
REQUIRED
Figure 4-2. IRQ Function Block Diagram
NOTE:
When the edge- and level-sensitive mask option is selected, the voltage
applied to the IRQ pin must return to the high state before the RTI
instruction in the interrupt service routine is executed to avoid the
processor re-entering the IRQ service routine.
The IRQ pin is one source of an IRQ interrupt, and a mask option can
also enable the port A pins (PA0–PA7) to act as other IRQ interrupt
sources. These sources are all combined into a single ORing function to
be latched by the IRQ latch.
Any enabled IRQ interrupt source sets the IRQ latch on the falling edge
of the IRQ pin or a port A pin if port A interrupts have been enabled. If
edge-only sensitivity is chosen by a mask option, only the IRQ latch
output can activate a request to the CPU to generate the IRQ interrupt
sequence. This makes the IRQ interrupt sensitive to the following cases:
1. Falling edge on the IRQ pin with all enabled port A interrupt pins
at a high level.
2. Falling edge on any enabled port A interrupt pin with all other
enabled port A interrupt pins and the IRQ pin at a high level.
IRQ
LATCH
R
VDD
IRQ PIN
MASK OPTION
(IRQ LEVEL)
TO IRQ
PROCESSING
IN CPU
TO BIH & BIL
INSTRUCTION
SENSING
RST
IRQ VECTOR FETCH
PA7
DDRA7
PA0
DDRA0
PA0 IRQ INHIBIT
(MASK OPTION)
PA7 IRQ INHIBIT
(MASK OPTION)
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| MC68HC05P3CP | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
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