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參數(shù)資料
| 型號： | MC68HSC05P1ADWR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 91/124頁 |
| 文件大?。?/td> | 623K |
| 代理商： | MC68HSC05P1ADWR2 |
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16-Bit Timer
Output Compare
MC68HC05P1A — Rev. 3.0
General Release Specification
MOTOROLA
16-Bit Timer
69
NON-DISCLOSURE
AGREEMENT
REQUIRED
After a CPU write cycle to the MSB of the output compare register pair
(OCRH), the output compare function is inhibited until the LSB (OCRL)
is written. Both bytes must be written if the MSB is written. A write made
only to the LSB will not inhibit the compare function. The free-running
counter increments every four PH2 clock cycles. The minimum time
required to update the output compare registers is a function of software
rather than hardware.
The output compare output level bit (OLVL) will be clocked to its output
latch regardless of the state of the output compare flag bit (OCF). A valid
output compare must occur before the OLVL bit is clocked to its output
latch (TCMP).
Since neither the output compare flag (OCF) nor the output compare
registers are affected by reset, care must be exercised when initializing
the output compare function. This procedure is recommended:
1. Block interrupts by setting the I bit in the condition code register
(CCR).
2. Write the MSB of the output compare register pair (OCRH) to
inhibit further compares until the LSB is written.
3. Read the timer status register (TSR) to arm the output compare
flag (OCF).
4. Write the LSB of the output compare register pair (OCRL) to
enable the output compare function and to clear its flag (and
interrupt).
5. Unblock interrupts by clearing the I bit in the CCR.
This procedure prevents the output compare flag bit (OCF) from being
set between the time it is read and the time the output compare registers
are updated. A software example is shown in Figure 8-7 and a state
timing diagram is shown in Figure 8-8.
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