參數(shù)資料
型號(hào)： MC80C52TXXX-16SC
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40
文件頁(yè)數(shù)： 37/77頁(yè)
文件大?。?/td> 7480K
代理商： MC80C52TXXX-16SC
42
SAMA5D3 Series [DATASHEET]
11121D–ATARM–03-Apr-14
Thumb state:
The processor executes 16-bit and 32-bit, halfword-aligned Thumb instructions.
ThumbEE state:
The processor executes a variant of the Thumb instruction set designed as a target for dynamically generated
code. This is code compiled on the device either shortly before or during execution from a portable bytecode or
other intermediate or native representation.
Jazelle state:
The processor executes variable length, byte-aligned Java bytecodes.
The J bit and the T bit determine the instruction set used by the processor. Table 10-1 shows the encoding of these bits.
Changing between ARM and Thumb states does not affect the processor mode or the register contents. See the ARM
Architecture Reference Manual for information on entering and exiting ThumbEE state.
10.4.2.1 Switching State
It is possible to change the instruction set state of the processor between:
ARM state and Thumb state using the BX and BLX instructions.
Thumb state and ThumbEE state using the ENTERX and LEAVEX instructions.
ARM and Jazelle state using the BXJ instruction.
Thumb and Jazelle state using the BXJ instruction.
See the ARM Architecture Reference Manual for more information about changing instruction set state.
10.4.3 Cortex-A5 Registers
This view provides 16 ARM core registers, R0 to R15, that include the Stack Pointer (SP), Link Register (LR), and
Program Counter (PC). These registers are selected from a total set of either 31 or 33 registers, depending on whether or
not the Security Extensions are implemented. The current execution mode determines the selected set of registers, as
shown in Table 10-2. This shows that the arrangement of the registers provides duplicate copies of some registers, with
the current register selected by the execution mode. This arrangement is described as banking of the registers, and the
duplicated copies of registers are referred to as banked registers.
Table 10-1. CPSR J and T Bit Encoding
J
T
Instruction Set State
00
ARM
0
1
Thumb
1
0
Jazelle
1
ThumbEE
Table 10-2. Cortex-A5 Modes and Registers Layout
User and
System
Monitor
Supervisor
Abort
Undefined
Interrupt
Fast
Interrupt
R0
R1
R2
R3
R4
R5
R6
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