參數(shù)資料
型號(hào)： MC80C52TXXX-16SC
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40
文件頁(yè)數(shù)： 59/77頁(yè)
文件大小： 7480K
代理商： MC80C52TXXX-16SC
62
SAMA5D3 Series [DATASHEET]
11121D–ATARM–03-Apr-14
12.
Standard Boot Strategies
12.1
Description
The system always boots from the ROM memory at address 0x0.
The ROM code is a boot program contained in the embedded ROM. It is also called “First level bootloader”.
By default, the chip starts in Standard Boot Mode.
Note:
JTAG access is disabled during the execution of ROM Code Sequence. It is re-enabled when jumping into
SRAM when a valid code has been found on an external NVM, in the same time the ROM memory is hidden. If
no valid boot has been found on an external NVM, the ROM Code enables the USB connection and the DBGU
serial port, and then waits for a special command to set the chip in Secure mode. If any other character is
received, the ROM code starts the standard SAM-BA monitor, locks access to the ROM memory and re-enables
the JTAG connection.
The user can choose to boot from an external NOR Flash memory using the BMS pin. The sampling of the BMS pin is
done by hardware at reset, and the result is available in the BMS_EBI bit of the SFR_EBICFG register.
The first step of the ROM code program is to check the state of this pin by reading this register.
If BMS signal is tied to 0, BMS_BIT is read at 1
The ROM code allows execution of the code contained intthe memory connected to Chip Select 0 of the External Bus
Interface.
To do so, the following sequence is performed by the ROM code:
The main clock is the on-chip 12 MHz RC oscillator.
The Static Memory Controller is configured with timing allowing code execution inCS0 external memory at 12 MHz.
AXI matrix is configured to remap EBI CS0 address at 0x0.
0x0 is loaded in the Program Counter register.
The user software in the external memory must perform the next operation in order to complete the clocks and SMC
timings configuration to run at a higher clock frequency:
Enable the 32768 Hz oscillator if best accuracy is needed.
Reprogram the SMC setup, cycle, hold, mode timing registers for EBI CS0, to adapt them to the new clock.
Program the PMC (Main Oscillator Enable or Bypass mode).
Program and start the PLL.
Switch the system clock to the new value.
If BMS signal is tied to 1, BMS_BIT is read at 0.
The ROM code standard sequence is executed as follows:
Basic chip initialization: crystal or external clock frequency detection.
Attempt to retrieve a valid code from external non-volatile memories (NVM).
Execution of a monitor called SAM-BA Monitor, in case no valid application has been found on any NVM.
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