參數(shù)資料
型號(hào)： MC80C52TXXX-16SC
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40
文件頁(yè)數(shù)： 43/77頁(yè)
文件大?。?/td> 7480K
代理商： MC80C52TXXX-16SC
48
SAMA5D3 Series [DATASHEET]
11121D–ATARM–03-Apr-14
10.5
Memory Management Unit
10.5.1 About the MMU
The MMU works with the L1 and L2 memory system to translate virtual addresses to physical addresses. It also controls
accesses to and from external memory.
The ARM v7 Virtual Memory System Architecture (VMSA) features include the following:
Page table entries that support:
16-Mbyte supersections. The processor supports supersections that consist of 16-Mbyte blocks of memory.
1-Mbyte sections
64-Kbyte large pages
4-Kbyte small pages
16 access domains
Global and application-specific identifiers to remove the requirement for context switch TLB flushes.
Extended permissions checking capability.
TLB maintenance and configuration operations are controlled through a dedicated coprocessor, CP15, integrated with
the core. This coprocessor provides a standard mechanism for configuring the L1 memory system.
See the ARM Architecture Reference Manual for a full architectural description of the ARMv7 VMSA.
10.5.2 Memory Management System
The Cortex-A5 processor supports the ARM v7 VMSA The translation of a Virtual Address (VA) used by the instruction
set architecture to a Physical Address (PA) used in the memory system and the management of the associated attributes
and permissions is carried out using a two-level MMU.
The first level MMU uses a Harvard design with separate micro TLB structures in the PFU for instruction fetches (IuTLB)
and in the DPU for data read and write requests (DuTLB).
A miss in the micro TLB results in a request to the main unified TLB shared between the data and instruction sides of the
memory system. The TLB consists of a 128-entry two-way set-associative RAM based structure. The TLB page-walk
mechanism supports page descriptors held in the L1 data cache. The caching of page descriptors is configured globally
for each translation table base register, TTBRx, in the system coprocessor, CP15.
The TLB contains a hitmap cache of the page types which have already been stored in the TLB.
10.5.2.1 Memory types
Although various different memory types can be specified in the page tables, the Cortex-A5 processor does not
implement all possible combinations:
Write-through caches are not supported. Any memory marked as write-through is treated as Non-cacheable.
The outer shareable attribute is not supported. Anything marked as outer shareable is treated in the same way as
inner shareable.
Write-back no write-allocate is not supported. It is treated as write-back write-allocate.
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