![](http://datasheet.mmic.net.cn/170000/MC80C52TXXX-16SC_datasheet_9174720/MC80C52TXXX-16SC_13.png)
13
SAMA5D3 Series [DATASHEET]
11121D–ATARM–03-Apr-14
D5
VDDIOP0
GPIO
PC21
I/O
—
RD0
I
—
PIO, I, PU, ST
C2
VDDIOP0
GPIO
PC22
I/O
—
SPI1_MISO
I/O
—
PIO, I, PU, ST
G9
VDDIOP0
GPIO
PC23
I/O
—
SPI1_MOSI
I/O
—
PIO, I, PU, ST
C1
VDDIOP0
GPIO_CLK
PC24
I/O
—
SPI1_SPCK
I/O
—
PIO, I, PU, ST
H10
VDDIOP0
GPIO
PC25
I/O
—
SPI1_NPCS0
I/O
—
PIO, I, PU, ST
H9
VDDIOP0
GPIO
PC26
I/O
—
SPI1_NPCS1
O
TWD1
I/O
ISI_D11
I
PIO, I, PU, ST
D4
VDDIOP0
GPIO
PC27
I/O
—
SPI1_NPCS2
O
TWCK1
O
ISI_D10
I
PIO, I, PU, ST
H8
VDDIOP0
GPIO
PC28
I/O
—
SPI1_NPCS3
O
PWMFI0
I
ISI_D9
I
PIO, I, PU, ST
G5
VDDIOP0
GPIO
PC29
I/O
—
URXD0
I
PWMFI2
I
ISI_D8
I
PIO, I, PU, ST
D3
VDDIOP0
GPIO
PC30
I/O
—
UTXD0
O
—
ISI_PCK
O
PIO, I, PU, ST
E4
VDDIOP0
GPIO
PC31
I/O
—
FIQ
I
PWMFI1
I
—
PIO, I, PU, ST
K5
VDDIOP1
GPIO
PD0
I/O
—
MCI0_CDA
I/O
—
PIO, I, PU, ST
P1
VDDIOP1
GPIO
PD1
I/O
—
MCI0_DA0
I/O
—
PIO, I, PU, ST
K6
VDDIOP1
GPIO
PD2
I/O
—
MCI0_DA1
I/O
—
PIO, I, PU, ST
R1
VDDIOP1
GPIO
PD3
I/O
—
MCI0_DA2
I/O
—
PIO, I, PU, ST
L7
VDDIOP1
GPIO
PD4
I/O
—
MCI0_DA3
I/O
—
PIO, I, PU, ST
P2
VDDIOP1
GPIO
PD5
I/O
—
MCI0_DA4
I/O
TIOA0
I/O
PWMH2
O
PIO, I, PU, ST
L8
VDDIOP1
GPIO
PD6
I/O
—
MCI0_DA5
I/O
TIOB0
I/O
PWML2
O
PIO, I, PU, ST
R2
VDDIOP1
GPIO
PD7
I/O
—
MCI0_DA6
I/O
TCLK0
I
PWMH3
O
PIO, I, PU, ST
K7
VDDIOP1
GPIO
PD8
I/O
—
MCI0_DA7
I/O
—
PWML3
O
PIO, I, PU, ST
U2
VDDIOP1
MCI_CLK
PD9
I/O
—
MCI0_CK
I/O
—
PIO, I, PU, ST
K9
VDDIOP1
GPIO
PD10
I/O
—
SPI0_MISO
I/O
—
PIO, I, PU, ST
M5
VDDIOP1
GPIO
PD11
I/O
—
SPI0_MOSI
I/O
—
PIO, I, PU, ST
K10
VDDIOP1
GPIO_CLK
PD12
I/O
—
SPI0_SPCK
I/O
—
PIO, I, PU, ST
N4
VDDIOP1
GPIO
PD13
I/O
—
SPI0_NPCS0
I/O
—
PIO, I, PU, ST
L9
VDDIOP1
GPIO
PD14
I/O
—
SCK0
I/O
SPI0_NPCS1
O
CANRX0
I
PIO, I, PU, ST
N3
VDDIOP1
GPIO
PD15
I/O
—
CTS0
I
SPI0_NPCS2
O
CANTX0
O
PIO, I, PU, ST
L10
VDDIOP1
GPIO
PD16
I/O
—
RTS0
O
SPI0_NPCS3
O
PWMFI3
I
PIO, I, PU, ST
N5
VDDIOP1
GPIO
PD17
I/O
—
RXD0
I
—
PIO, I, PU, ST
M6
VDDIOP1
GPIO
PD18
I/O
—
TXD0
O
—
PIO, I, PU, ST
T1
VDDIOP1
GPIO
PD19
I/O
—
ADTRG
I
—
PIO, I, PU, ST
N2
VDDANA
GPIO_ANA
PD20
I/O
—
AD0
I
—
PIO, I, PU, ST
M3
VDDANA
GPIO_ANA
PD21
I/O
—
AD1
I
—
PIO, I, PU, ST
M2
VDDANA
GPIO_ANA
PD22
I/O
—
AD2
I
—
PIO, I, PU, ST
L3
VDDANA
GPIO_ANA
PD23
I/O
—
AD3
I
—
PIO, I, PU, ST
M1
VDDANA
GPIO_ANA
PD24
I/O
—
AD4
I
—
PIO, I, PU, ST
N1
VDDANA
GPIO_ANA
PD25
I/O
—
AD5
I
—
PIO, I, PU, ST
L1
VDDANA
GPIO_ANA
PD26
I/O
—
AD6
I
—
PIO, I, PU, ST
L2
VDDANA
GPIO_ANA
PD27
I/O
—
AD7
I
—
PIO, I, PU, ST
K1
VDDANA
GPIO_ANA
PD28
I/O
—
AD8
I
—
PIO, I, PU, ST
K2
VDDANA
GPIO_ANA
PD29
I/O
—
AD9
I
—
PIO, I, PU, ST
J1
VDDANA
GPIO_ANA
PD30
I/O
—
AD10
I
PCK0
O
—
PIO, I, PU, ST
J2
VDDANA
GPIO_ANA
PD31
I/O
—
AD11
I
PCK1
O
—
PIO, I, PU, ST
Table 4-1.
SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)
Pin
Power Rail
I/O Type
Primary
Alternate
PIO Peripheral A
PIO Peripheral B
PIO Peripheral C
Reset State
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal, Dir,
PU, PD, HiZ,
ST