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參數(shù)資料
| 型號： | MC80C52TXXX-16SC |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁數(shù)： | 38/77頁 |
| 文件大?。?/td> | 7480K |
| 代理商： | MC80C52TXXX-16SC |
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43
SAMA5D3 Series [DATASHEET]
11121D–ATARM–03-Apr-14
The core contains one CPSR, and six SPSRs for exception handlers to use. The program status registers:
hold information about the most recently performed ALU operation
control the enabling and disabling of interrupts
set the processor operation mode
Figure 10-2. Status Register Format
N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags
Q: cumulative saturation flag
IT: If-Then execution state bits for the Thumb IT (If-Then) instruction
J: Jazelle bit, see the description of the T bit
GE: Greater than or Equal flags, for SIMD instructions
E: Endianness execution state bit. Controls the load and store endianness for data accesses. This bit is ignored by
instruction fetches.
E = 0: Little endian operation
E = 1: Big endian operation
A: Asynchronous abort disable bit. Used to mask asynchronous aborts.
I: Interrupt disable bit. Used to mask IRQ interrupts.
F: Fast interrupt disable bit. Used to mask FIQ interrupts.
T: Thumb execution state bit. This bit and the J execution state bit, bit [24], determine the instruction set state of
the processor, ARM, Thumb, Jazelle, or ThumbEE.
R7
R8
R8_FIQ
R9
R9_FIQ
R10
R10_FIQ
R11
R11_FIQ
R12
R12_FIQ
R13
R13_MON
R13_SVC
R13_ABT
R13_UND
R13_IRQ
R13_FIQ
R14
R14_MON
R14_SVC
R14_ABT
R14_UND
R14_IRQ
R14_FIQ
PC
CPSR
SPSR_MON
SPSR_SVC
SPSR_ABT
SPSR_UND
SPSR_IRQ
SPSR_FIQ
Mode-specific banked registers
Table 10-2. Cortex-A5 Modes and Registers Layout (Continued)
User and
System
Monitor
Supervisor
Abort
Undefined
Interrupt
Fast
Interrupt
NZ C V Q
JI F T
Mode
Reserved
31 30 29 28 27
24
7 6 5
0
IT
[1:0]
8
9
10
15
16
20 19
23
4
IT[7:2]
GE[3:0]
A
E
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