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| 型號(hào)： | MC92600CJUB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA217 |
| 封裝： | 23 X 23 MM, 2.32 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-217 |
| 文件頁數(shù)： | 29/98頁 |
| 文件大?。?/td> | 1288K |
| 代理商： | MC92600CJUB |
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MOTOROLA
Chapter 3. Receiver
3-7
Alignment Modes
3.3.2.1
Word Synchronization Method
Word synchronization aligns characters in the receiver’s alignment FIFO. Synchronization
is accomplished by lining up word synchronization events detected by each of the receivers,
such that all are coincident at the same stage of their FIFO.
A word synchronization event is dened differently depending on the state of the
BSYNC_0 and BSYNC_1 signals. Table 3-3 shows the type of word synchronization event
used.
There are two types of word synchronization events: the 4/1 idle sequence and the
disparity-based idle sequence.
The 4/1 idle sequence is dened as four consecutive idle characters followed by a
non-idle character.
The disparity-based idle sequence is 16 consecutive idle characters with improper
disparity on the second and fourth idle character in the sequence. The
disparity-based idle sequence is described further in Section 2.4.1, “Transmitting
Word synchronization events must be generated at all concerned transmitters
simultaneously in order for synchronization to be achieved. Word synchronization events
must be received at all concerned receivers within 40 bit-times of each other.
Word synchronization events are used to establish a relationship between the received bytes
in each of the receivers. The bytes of a word are matched and presented simultaneously at
the receiver interface. Once synchronization is achieved, the receiver tolerates +/- 6
bit-times of drift between receivers. If drift exceeds +/- 6 bit-times, the receiver will
continue to operate. However, the received bytes will no longer be synchronized properly
because the receiver remains locked onto the initially established synchronization. Word
synchronization remains locked until one of three events occurs that indicate loss of
synchronization.
Word synchronization lock can be lost in three ways:
When one or more of the receivers lose or change byte alignment. Byte alignment
loss is described in Section 3.3.1.1, “Byte-Aligned with Realignment.”
When overrun/underrun is detected on one or more of the receivers but not on all
simultaneously, see Section 3.4.2, “Reference Clock Timing Mode” for more about
overrun/underrun.
Table 3-3. Word Synchronization Events
Word Synchronization Event
BSYNC_0
BSYNC_1
4 idle/1 non-idle
Low
don’t care
Disparity-based idle sequence
High
Low
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For More Information On This Product,
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| MC92600JUB | 功能描述:IC SERDES QUAD 1.25GBAUD 217PBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:管件 |
| MC92600VMB | 制造商:Freescale Semiconductor 功能描述: |
| MC92603VF | 功能描述:IC TXRX ETH QUAD GIG 256-MAPBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:25 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-PDIP 包裝:管件 |
| MC92603VM | 功能描述:IC ETH TXRX QUAD GIG 256-MAPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| MC92604VM | 功能描述:IC ETH TXRX DUAL GIG 196-MAPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
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