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參數(shù)資料
| 型號： | MC92600CJUB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA217 |
| 封裝： | 23 X 23 MM, 2.32 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-217 |
| 文件頁數(shù)： | 49/98頁 |
| 文件大?。?/td> | 1288K |
| 代理商： | MC92600CJUB |
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MOTOROLA
Chapter 5. Test Features
5-3
Loop Back BIST Sequence System Test Mode
The BIST sequence makes use of the 8B/10B encoder/decoder. Therefore, this test mode
overrides the setting on TBIE signal and forces byte interface mode. Additionally, the BIST
sequence requires that a normal byte alignment mode be used. The settings on BSYNC_0
and BSYNC_1 are overridden, forcing the device into the byte aligned with realignment
mode. In addition to the above signals, the generation of disparity-based word
synchronization events is blocked. The WSE_GEN signal is ignored when this test mode is
enabled.
BIST is run at the speed indicated by the frequency of the reference clock and by the speed
range selected by half-speed mode (HSE). The settings of DDRE, WSE and RCCE are not
altered and BIST will follow their setting
5.3
Loop Back BIST Sequence System Test Mode
This test mode is the combination of the loop back and BIST sequence system test modes.
The device operates as described in Section 5.1, “Loop Back System Test” and Section 5.2,
“BIST Sequence System Test Mode.” However, the need to go through the start-up
sequence is eliminated because the transmitter automatically goes through the proper
sequence.
5.4
Board Level Manufacturing Test Mode
In this test mode all TTL output drivers (all data outputs, status outputs, and recovered clock
outputs) are placed in a high impedance state to facilitate common board level
manufacturing testing practices.
Note, however, that the transmitter link output drivers are still active.
In normal operational modes (TST_0, TST_1 and LBE all low), LBOE must also be low.
If LBOE is high, the transmitters will be functioning properly, however, the receivers will
appear to be non-functional because all TTL output drivers are in a high impedance state.
Table 5-2. BIST Error Codes
RECV_x_ERR
RECV_x_K
RECV_x_IDLE
Description
Low
BIST running, no PN mismatch this character.
High
Low
BIST running, PN mismatch error this character.
High
Low
High
Receiver byte/word synchronized, PN analyzer is not locked.
High
Low
Not byte sync—The receiver is in start-up or has lost byte
alignment and is searching for alignment.
High
Not word sync—The receiver is byte synchronized but has not
achieved or has lost word alignment and is searching for
alignment.
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