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參數(shù)資料
| 型號(hào)： | MC92600CJUB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA217 |
| 封裝： | 23 X 23 MM, 2.32 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-217 |
| 文件頁(yè)數(shù)： | 35/98頁(yè) |
| 文件大?。?/td> | 1288K |
| 代理商： | MC92600CJUB |
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3-12
MC92600 SERDES User’s Manual
MOTOROLA
Device Operations
3.5.4
Receiver Interface Modes
The receiver interface facilitates transfer of received data to the system. It also provides
information on the status of the link. Table 3-1, "MC92600 Receiver Interface Signals,”
describes each of the signals involved in receiver operation.
The receiver interface, through which received data is obtained, may be operated in byte
mode or in 10-bit interface mode. Several timing mode options exist for the receiver
interface. Each of the operating modes are described in the following sections.
3.5.4.1
Byte Interface Mode
The receiver interface may be operated in byte mode or in 10-bit interface (TBI) mode.
Received data is a byte (8 bits) of uncoded data when in byte mode. Byte interface mode is
enabled by setting the TBIE signal low.
NOTE
Do not use non-aligned mode in byte interface mode. See
Section 3.3.1, “Byte Alignment” for more information on byte
alignment modes.
The internal 8B/10B decoder is used to decode data from the 10-bit character received. The
received byte is on the RECV_x_7 through RECV_x_0 signals.
The RECV_x_K is asserted when the byte represents a special 8B/10B code, otherwise it
is low, indicating that the byte is normal data.
The RECV_x_IDLE is asserted when the byte is the special 8B/10B idle (K28.5) code. This
can be used by system logic for synchronization or data parsing. RECV_x_IDLE is set low
when the byte is normal data or a non-idle special code. RECV_x_IDLE is asserted and
RECV_x_K is set low to indicate that an underrun/overrun error occurred. See Section 3.6,
“Receiver Interface Error Codes” for more information on error conditions.
The RECV_x_ERR is set low when the receiver is operating normally, and is asserted when
received data contains an error or the receiver is in an error state. The state of the
RECV_x_IDLE and RECV_x_K signals are decoded to determine the error condition.
Table 3.6, "Receiver Interface Error Codes” describes the error codes and their meaning.
The receiver interface is timed to the recovered clock, RECV_x_RCLK, or to the reference
clock, REF_CLK, depending on the state of the RCCE signal.
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