參數資料
型號: MC92600CJUB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA217
封裝: 23 X 23 MM, 2.32 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-217
文件頁數: 58/98頁
文件大小: 1288K
代理商: MC92600CJUB
MOTOROLA
Chapter 6. Electrical Specications and Characteristics
6-7
AC Electrical Characteristics
)
6.3.1.5
Receiver (DDRE = Low, RCCE = High)
The receiver timing diagram for DDRE = Low, RCCE = High is shown in Figure 6-5.
Figure 6-5. Receiver Interface Timing Diagram (DDRE = Low, RCCE = High
Table 6-9 shows the timing specications for DDRE = Low, RCCE = High.
Table 6-9. Receiver Timing Specication (DDRE = Low, RCCE = High)
6.3.1.6
Receiver (DDRE = High, RCCE = High)
The receiver timing diagram for DDRE = High, RCCE = High is shown in Figure 6-6.
Table 6-8. Receiver Timing Specication (DDRE = High, RCCE = Low
Symbol
Characteristic
Min
Max
Unit
T1
Output valid time before rising/falling edge of REF_CLK 1, 2
Output valid time before rising/falling edge of REF_CLK1, 3
1
REF_CLK duty cycle 45/55.
2 Full speed, HSE = Low.
3 Half speed, HSE = High.
2.2
-
ns
10.2
-
ns
T2
Output valid time after rising/falling edge of REF_CLK2,3, 4
Output valid time after rising/falling edge of REF_CLK2,3, 5
4 Operating Junction Temperature, T
J = 0 to +105
oC
5 Operating Junction Temperature, T
J = -40 to +105
oC
2.0
-
ns
1.744
-
ns
Symbol
Characteristic
Min
Max
Unit
T1
Output valid time before rising edge of RECV_x_RCLK 1
Output valid time before rising edge of RECV_x_RCLK 2
1 Full speed, HSE = Low.
2 Half speed, HSE = High.
2.5
ns
5.7
ns
T2
Output valid time after rising edge of RECV_x_RCLK1
Output valid time after rising edge of RECV_x_RCLK2
3.4
ns
6.6
ns
T1
T2
RECV_x_RCLK
RECV_x_7–0
RECV_x_K
RECV_x_IDLE
RECV_x_ERR
RECV_x_9
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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