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參數(shù)資料
| 型號： | MCZ33927EK |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Transistor; Type: Amplifiers/Bipolar; VCEO (V): -100; Ic (A): -1; Pc (W): 0.9; hFE: 140 to 350; VCE (sat) (V) max: -0.5; Package: TO-92Mod |
| 中文描述： | 三相場效應(yīng)晶體管預(yù)驅(qū)動器 |
| 文件頁數(shù)： | 28/44頁 |
| 文件大小： | 490K |
| 代理商： | MCZ33927EK |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
28
33927
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
RESET AND ENABLE
The 33927 has three power modes of operation described
in
Table 5
. There are three global control inputs (RST, EN1,
EN2), which together with the status of the VDD and VLS,
control the behavior of the IC.
The operating status of the IC can be described by the
following three modes:
Sleep Mode
- When RST is low, the IC is in Sleep Mode.
The current consumption of the IC is at minimum.
Standby Mode
- The RST input is high while one of the
Enable inputs is low. The IC is fully biased up and
operating, all the external FETs are actively turned off
by both high-side and low-side gate drives. The IC is
ready to enter the Enable Mode.
Enable Mode
- In order to enter the Enable Mode
(normal mode of operation), and to operate the outputs,
the RST input must be high, and both Enable inputs
EN1 and EN2 must also be high.
After entry to Enable Mode, the IC requires a pulse on
Px_LS in order to charge the bootstrap capacitor before
allowing the Px_HS to turn on. This pulse should be
about 50 μs to guarantee the bootstrap capacitor is
charged, but the IC does not enforce this condition. If
there is an alternate means of pre-charging the
bootstrap capacitor, i.e. an external resistor from
Px_HS_S to GND, then a very brief pulse of 1.0 μs is
sufficient to reset the logic.
Table 5. Functions of RST, EN1 and EN2 Pins
RST
EN1, EN2
Mode of Operation (Driver Condition)
0
xx
Sleep Mode
- in this mode (low quiescent current) the driver output stage is switched-off with a weak pull-down. All error
and SPI registers are cleared. The internal 5.0V regulator is turned off and VDD is pulled low. Logic outputs are clamped
to GND.
1
0x
x0
Standby Mode
- IC fully biased up and all functions are operating, the output drivers actively turn off all of the external
FETs. The SPI port is functional. Logic level outputs are driven with low impedance. V
DD
, Charge Pump and V
LS
regulators are all operating. The IC is ready to move to Enable Mode.
1
11
Enable Mode
- (normal operation). Drivers are enabled; output stages follow the input command. After Enable, outputs
require a pulse on Px_LS before corresponding HS outputs will turn on in order to recharge bootstrap capacitor. All error
pin and register bits are active if detected.
Table 6. Functional Ratings
(
T
J
=-40°C to 150°C and supply voltage range V
BAT
= V
PWR
= 5.0V to 45V, C = 0.47μF)
Characteristic
Value
Default State of input pin Px_LS, EN1, EN2, RST, SI, SCLK, if left open
(49)
(Driver output is switched off, high impedance mode)
Low (<1.0V)
Default State of input pin Px_HS, CS if left open
(49)
(Driver output is switched off, high impedance mode)
High (>2.0V)
Notes
49.
To assure a defined status for all inputs, these pins are internally biased by pull-up/down current sources.
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