參數(shù)資料
型號: MCZ33927EK
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Transistor; Type: Amplifiers/Bipolar; VCEO (V): -100; Ic (A): -1; Pc (W): 0.9; hFE: 140 to 350; VCE (sat) (V) max: -0.5; Package: TO-92Mod
中文描述: 三相場效應(yīng)晶體管預(yù)驅(qū)動器
文件頁數(shù): 30/44頁
文件大?。?/td> 490K
代理商: MCZ33927EK
Analog Integrated Circuit Device Data
Freescale Semiconductor
30
33927
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
NULL COMMANDS
This command is sent by sending binary 000x xxxx data. This can be used to read IC status in the SPI return word. Message
000x xx00 reads Status Register 0. Message 000x xx01 through 000x xx11 read additional internal registers.
MASK Command
This is the mask for interrupts. A bit set to “1” enables the corresponding interrupt. Because of the number of MASK bits, this
register is in two portions:
1. MASK0
2. MASK1
Both are accessed with 0010 xxxx and 0011 xxxx patterns respectively.
Figure
illustrates how interrupts are enabled and faults
cleared.
CLINT0 and CLINT1 have the same format as MASK0 and MASK1 respectively, but the action is to clear the interrupt latch
and status register 0 bit corresponding to the lower nibble of the command.
INTERRUPT HANDLING
Figure 15. Interrupt Handling
Table 8. NULL Commands
SPI Data Bits
7
6
5
4
3
2
1
0
Write
0
0
0
x
x
x
0
0
Reset
NULL Commands are described in detail in the STATUS REGISTERS section of this document.
Table 9. MASK0 Register
SPI Data Bits
7
6
5
4
3
2
1
0
Write
0
0
1
0
x
x
x
x
Reset
1
1
1
1
Table 10. MASK1 Register
SPI Data Bits
7
6
5
4
3
2
1
0
Write
0
0
1
1
x
x
x
x
Reset
1
1
1
1
To Status Register
Various Faults
From Clint Command
From MASKx:N Register
Fault
net 0
net N
INT
M
INT Clear
INT Source
S
R
Latch
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