參數(shù)資料
型號(hào)： MCZ33927EK
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Transistor; Type: Amplifiers/Bipolar; VCEO (V): -100; Ic (A): -1; Pc (W): 0.9; hFE: 140 to 350; VCE (sat) (V) max: -0.5; Package: TO-92Mod
中文描述： 三相場(chǎng)效應(yīng)晶體管預(yù)驅(qū)動(dòng)器
文件頁數(shù)： 33/44頁
文件大?。?/td> 490K
代理商： MCZ33927EK
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
33927
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
STATUS REGISTERS
After any SPI command, the status of the IC is reported in
the return value from the SPI port. There are four variants of
the NULL command used to read various status in the IC.
Other commands return a general status word in the Status
Register 0.
There are four Status Registers in the IC. Status
Register 0 is most commonly used for general status.
Registers one through three are used to read or confirm
internal IC settings.
Status Register 0 (Status Latch Bits)
This register is read by sending the NULL0 command (000x xx00). It is also returned after any other command. This command
returns the following data:
Table 14. Status Register 0
SPI Data Bits
7
6
5
4
3
2
1
0
Results
Register 0
Read
RESET
Event
Write
Error
Framing
Error
Phase
Error
Overcurrent
Low
VLS
DESAT
Detected on
any Channel
TLIM
Detected on
any Channel
Reset
1
0
0
0
0
0
0
0
All status bits are latched. The latches are cleared only by sending a CLINT0 or CLINT1 command with the appropriate bits
set. If the status is still present, that bit will not clear. CLINT0 and CLINT1 have the same format as MASK0 and MASK1
respectively.
Bit 0
–is a flag for
Overtemperature
on any channel. This bit is the OR of the latched three internal TLIM detectors.This
flag can generate an interrupt if the appropriate mask bit is set.
Bit 1
–is a flag for
Desaturation Detection
on any channel. This bit is the OR of the latched three internal high-side
desaturation detectors and phase error logic. Faults are also detected on the low-side as
phase errors.
A phase error is
generated if the output signal (at Px_HS_S) does not properly reflect the drive conditions. The phase error is the triple OR
of phase errors from each phase. Each phase error is the OR of the HS and LS phase errors. An HS phase error (which
will also trigger the desaturation detector) occurs when the HS FET is commanded on, and the Px_HS_S is still
low
in the
deadtime duration after it is driven ON. Similarly, a LS phase error occurs when the LS FET is commanded on, and the
Px_HS_S is still
high
in the deadtime duration after the FET is driven ON. This flag can generate an interrupt if the
appropriate mask bit is set.
Bit 2
– is a flag for
Low Supply Voltage
. This bit is latched, thus a prior low voltage event is returned once before being
cleared on read. This flag can generate an interrupt if the appropriate mask bit is set.
Bit 3
–is a flag for the output of the
Overcurrent Comparator
. This flag can generate an interrupt if the appropriate mask
bit is set.
Bit 4
–is a flag for a
Phase Error
. If any Phase comparator output is not at the expected value when just one of the
individual high- or low-side outputs is enabled, the fault flag is set. This signal is the XOR of the phase comparator output
with the output driver state, and blanked for the duration of the desaturation blanking interval. This flag can generate an
interrupt if the appropriate mask bit is set.
Bit 5
–is a flag for a
Framing Error
. A framing error is a SPI message not a multiple of eight bits (a 0-length message is
also a framing error), or SI, or SCLK toggling detected while measuring the Deadtime calibration pulse. This would typically
be a transient or permanent hardware error, perhaps due to noise on the SPI lines. This flag can generate an interrupt if
the appropriate mask bit is set.
Bit 6
–indicates a
Write Error After the Lock
bit is set. A write error is any attempted write to the MASKn, Mode, or a
Deadtime command after the Mode Lock bit is set. A write error is any attempt to write any other command than the one
defined in the
Table 7
. This would typically be a software error. This flag can generate an interrupt if the appropriate mask
bit is set.
Bit 7
–is set upon
exiting RST
. It can be used to test the interrupt mechanism or to flag for a condition where the IC gets
reset without the host being otherwise aware. This flag can generate an interrupt if the appropriate mask bit is set.
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