
29
ATmega64A [DATASHEET]
8160D–AVR–02/2013
Bit 7 – XMBK: External Memory Bus Keeper Enable
Writing XMBK to one enables the Bus Keeper on the AD7:0 lines. When the Bus Keeper is enabled, it will ensure a
defined logic level (zero or one) on AD7:0 when they would otherwise be tri-stated. Writing XMBK to zero disables
still activated as long as XMBK is one.
Bit 6:3 – Res: Reserved Bits
These are reserved bits and will always read as zero. When writing to this address location, write these bits to zero
for compatibility with future devices.
Bit 2:0 – XMM2, XMM1, XMM0: External Memory High Mask
When the External Memory is enabled, all Port C pins are default used for the high address byte. If the full 60 Kbyte
address space is not required to access the external memory, some, or all, Port C pins can be released for normal
64 Kbyte” on page 24, it is possible to use the XMMn bits to access all 64 Kbyte locations of the external memory.
8.6.4
EEARH and EEARL – EEPROM Address Register
Bits 15:11 – Res: Reserved Bits
These are reserved bits and will always read as zero. When writing to this address location, write these bits to zero
for compatibility with future devices.
Bits 10:0 – EEAR10:0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 2 Kbytes EEPROM
space. The EEPROM data bytes are addressed linearly between 0 and 2,048. The Initial Value of EEAR is unde-
fined. A proper value must be written before the EEPROM may be accessed.
Table 8-4.
Port C Pins Released as Normal Port Pins when the External Memory is Enabled
XMM2
XMM1
XMM0
# Bits for External Memory Address
Released Port Pins
0
8 (Full 60 Kbyte space)
None
00
1
7
PC7
0
1
0
6
PC7 - PC6
0
1
5
PC7 - PC5
1
0
4
PC7 - PC4
1
0
1
3
PC7 - PC3
1
0
2
PC7 - PC2
1
No Address high bits
Full Port C
Bit
15141312
11
10
9
8
–
EEAR10
EEAR9
EEAR8
EEARH
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
EEARL
765
43
2
1
0
Read/Write
R
R/W
Initial Value
0
X
XXX
X