參數(shù)資料
型號: MH28D72KLG-10
廠商: Mitsubishi Electric Corporation
英文描述: 9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
中文描述: 9663676416位(134217728 - Word的72位),雙數(shù)據(jù)速率同步DRAM模塊
文件頁數(shù): 15/39頁
文件大?。?/td> 337K
代理商: MH28D72KLG-10
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0412-0.1
21.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
15
/CAS
Latency
Burst
Length
CL= 2
BL= 4
Burst
Length
A2
A1
A0
Initial Address BL
Sequential
Interleaved
Column Addressing
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
-
0
0
-
0
1
-
1
0
-
1
1
-
-
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
7
0
1
2
0
1
2
3
1
2
3
0
2
3
0
1
3
0
0
1
7
6
5
4
0
1
2
3
1
0
3
2
2
3
0
1
3
2
0
1
-
-
1
1
2
1
0
3
4
5
6
3
2
1
0
1
0
1
0
8
4
2
Command
Address
DQ
Y
Y
Read
Write
DQS
Q0 Q1 Q2 Q3
D0 D1 D2 D3
/CLK
CLK
( Componennt Level )
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