參數資料
型號： MH28D72KLG-10
廠商： Mitsubishi Electric Corporation
英文描述： 9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
中文描述： 9663676416位（134217728 - Word的72位），雙數據速率同步DRAM模塊
文件頁數： 35/39頁
文件大?。?/td> 337K
代理商： MH28D72KLG-10
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0412-0.1
21.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
35
Serial Presence Detect Table I
Byte
Function described
SPD enrty data
SPD DATA(hex)
0
Number of Serial PD Bytes Written during Production
128
80
1
Total # bytes of SPD memory device
256 Bytes
08
2
Fundamental memory type
SDRAM DDR
07
0D
0B
3
# Row Addresses on this assembly
13
11
4
# Column Addresses on this assembly
5
# Module Banks on this assembly
2BANK
02
6
Data Width of this assembly...
x72
0
48
7
... Data Width continuation
00
8
Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL).
SSTL2.5V
7.5ns
04
75
80
9
Cycle time for CL=2.5
10
SDRAM Access from Clock
tAC for CL=2.5
11
DIMM Configuration type (Non-parity,Parity,ECC)
ECC
02
82
12
13
Refresh Rate/Type
SDRAM width,Primary DRAM
x4
04
14
Error Checking SDRAM data width
MIimum Clock Delay, Random Column Access
x4
04
15
01
16
Burst Lengths Supported
Number of Device Banks
2, 4, 8
0E
04
0C
01
17
4bank
2.0, 2.5
0
18
19
CAS# Latency
CS# Latency
20
WE Latency
21
SDRAM Module Attributes
Registered with PLL
Differential Clock
26
22
SDRAM Device Attributes:General
VDD + 0.2V
00
23
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
24
SDRAM Access form Clock(2nd highest CAS latency)
80
tAC for CL=2
25
SDRAM Cycle time(3rd highest CAS latency)
26
SDRAM Access form Clock(3rd highest CAS latency)
27
Minimum Row Precharge Time (tRP)
15ns
50
28
Minimum Row Active to Row Active Delay (tRRD)
20ns
3C
8.0ns
-10
10ns
A0
75
-75
29
RAS to CAS Delay Minv (tRCD)
20ns
2D
30
Active to Precharge Min (tRAS)
32
+0.75ns
+0.8 ns
-75
-10
-75
-10
-75
-10
-75
-10
45ns
50ns
N/A
+0.75ns
+0.8ns
75
80
00
00
00
50
7.8uS/SR
1
02
1 clock
10ns
A0
-75
-10
-75
-10
N/A
00
N/A
N/A
相關PDF資料
PDF描述
MH28D72KLG-75 9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MH28S72PJG-5 Circular Connector; Body Material:Aluminum Alloy; Series:KPSE07; No. of Contacts:19; Connector Shell Size:14; Connecting Termination:Crimp; Circular Shell Style:Jam Nut Receptacle; Circular Contact Gender:Pin RoHS Compliant: No
MH28S72PJG-6 Circular Connector; Body Material:Aluminum Alloy; Series:KPSE07; No. of Contacts:19; Connector Shell Size:14; Connecting Termination:Crimp; Circular Shell Style:Jam Nut Receptacle; Circular Contact Gender:Socket RoHS Compliant: No
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相關代理商/技術參數
參數描述
MH28D72KLG-75 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MH28FAD 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator
MH28FAD-R 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator
MH28FAD-R-1.96608MHZ 制造商:MtronPTI 功能描述:
MH28FAD-R-32.000MHZ 制造商:MtronPTI 功能描述:
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