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參數(shù)資料
| 型號： | MH28D72KLG-75 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| 中文描述： | 9663676416位（134217728 - Word的72位），雙數(shù)據(jù)速率同步DRAM模塊 |
| 文件頁數(shù)： | 1/39頁 |
| 文件大?。?/td> | 337K |
| 代理商： | MH28D72KLG-75 |
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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0412-0.1
21.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
1
DESCRIPTION
APPLICATION
Main memory unit for PC, PC server, Server, W S.
FEATURES
Type name
133MHz
MH28D72KLG-10
MH28D72KLG-75
- Utilizes industry standard 64M X 4 DDR Synchronous DRAMs
in TSOP package , industry standard Registered Buffer in
TSSOP package , and industry standard PLL in TSSOP package.
-
Vdd=Vddq=2.5v±0.2V
- Double data rate architecture; two data transfers per
clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received
with data
- Differential clock inputs (CLK and /CLK)
- data referenced to both edges of DQS
- /CAS latency- 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11
- SSTL_2 Interface
- Module 2bank Configration
- Burst Type - sequential/interleave(programmable)
- Commands entered on each positive CLK edge
Max.
Frequency
100MHz
1pin
52pin
92pin
93pin
144pin
145pin
184pin
The MH28D72KLG is 134217728 - word x 72-bit Double
Data Rate(DDR) Synchronous DRAM mounted module.
This consists of 36 industry standard 64M x 4 DDR
Synchronous DRAMs in TSOP with SSTL_2 interface which
achieves very high speed data rate up to 133MHz.
This socket-type memory module is suitable for main
memory in computer systems and easy to interchange or
add modules.
CLK
Access Time
[component level]
53pin
+ 0.75ns
+ 0.8ns
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