參數(shù)資料
型號(hào)： MH28D72KLG-10
廠商： Mitsubishi Electric Corporation
英文描述： 9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
中文描述： 9663676416位（134217728 - Word的72位），雙數(shù)據(jù)速率同步DRAM模塊
文件頁(yè)數(shù)： 18/39頁(yè)
文件大?。?/td> 337K
代理商： MH28D72KLG-10
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0412-0.1
21.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
18
AC TIMING REQUIREMENTS
(Component Level)
(Ta=0 ~ 70°C , Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
ns
15
10
15
10
CL=2
ns
15
8
15
7.5
CL=2.5
19
19
20
ns
+0.6
+0.5
DQS-DQ Skew(for DQS and all DQ signals)
tDQSA
ns
min
(tCL,tCH)
min
(tCL,tCH)
CLK half period
tHP
tCK
0.55
0.45
0.55
0.45
CLK Low level width
tCL
CLK cycle time
tCK
16
15
14
14
AC Characteristics
-10
-75
1.1
0.9
1.1
0.9
0.6
0.4
0.6
0.4
1.1
0.9
1.1
0.9
0.25
0.25
0.6
0.4
0.6
0.4
0
0
15
15
0.2
0.2
0.2
0.2
0.35
0.35
0.35
0.35
1.25
0.75
1.25
0.75
tHP-1.0
tHP-0.75
+0.6
+0.5
+0.8
-0.8
+0.75
-0.75
+0.8
-0.8
+0.75
-0.75
2
1.75
tCK
tCK
ns
ns
tCK
tCK
ns
ns
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
0.6
0.5
0.6
0.5
tCK
0.45
0.55
0.45
+0.8
-0.8
+0.75
-0.75
+0.8
-0.8
+0.75
-0.75
Max.
Min.
Max.
Min.
Parameter
0.55
Read preamble
tRPRE
Read postamble
tRPST
tWPRE
Write preamble
tWPST
Write postamble
tWPRES
Write preamble setup time
Input Hold time (address and control)
tIH
tIS
Input Setup time (address and control)
tMRD
Mode Register Set command cycle time
tDSH
DQS falling edge hold time from CLK
tDSS
DQS falling edge to CLK setup time
tDQSL
DQS input Low level width
tDQSH
DQS input High level width
tDQSS
Write command to first DQS latching transition
tQH
DQ/DQS output hold time from DQS
tDQSQ
DQS-DQ Skew(for DQS and associated DQ signals)
Data-out-low impedance time from CLK//CLK
tLZ
tHZ
Data-out-high impedance time from CLK//CLK
tDIPW
DQ and DM input pulse width (for each input)
Input Hold time(DQ,DM)
Input Setup time (DQ,DM)
tDS
tDH
tCH
CLK High level width
ns
DQ Output Valid data delay time from CLK//CLK
tDQSCK
DQ Output Valid data delay time from CLK//CLK
ns
tAC
Notes
Unit
Symbol
相關(guān)PDF資料
PDF描述
MH28D72KLG-75 9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MH28S72PJG-5 Circular Connector; Body Material:Aluminum Alloy; Series:KPSE07; No. of Contacts:19; Connector Shell Size:14; Connecting Termination:Crimp; Circular Shell Style:Jam Nut Receptacle; Circular Contact Gender:Pin RoHS Compliant: No
MH28S72PJG-6 Circular Connector; Body Material:Aluminum Alloy; Series:KPSE07; No. of Contacts:19; Connector Shell Size:14; Connecting Termination:Crimp; Circular Shell Style:Jam Nut Receptacle; Circular Contact Gender:Socket RoHS Compliant: No
MH28S72PJG-7 KPSE 19C 19#20 SKT RECP
MH2M365CXJ-5 HYPER PAGE MODE 75497472-BIT ( 2097152-WORD BY 36-BIT ) DYNAMIC RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MH28D72KLG-75 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MH28FAD 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator
MH28FAD-R 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator
MH28FAD-R-1.96608MHZ 制造商:MtronPTI 功能描述:
MH28FAD-R-32.000MHZ 制造商:MtronPTI 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*