參數(shù)資料
型號: ML60851D
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: USB Device Controller
中文描述: USB設(shè)備控制器
文件頁數(shù): 61/82頁
文件大?。?/td> 705K
代理商: ML60851D
ML60851D
Semiconductor
61/82
PEDL60851D-01
Application Interface
Note:
1. Initial value immediately after resetting. Its assertion can be changed by programming.
Description
Assertion
Type
I/O
Signal
D15:D8
Upper byte (MSB) of data bus. This data bus is used by applications to access
register files and FIFO data.
Lower byte (LSB) of data bus when ADSEL is LOW.
Address and lower byte of data bus are multiplexed when ADSEL is HIGH.
Address when ADSEL is LOW. This address signal is used by application to
access register files and FIFO data.
This signal is ignored (all lows or all highs) when ADSEL is HIGH.
Chip Select. When this signal is asserted LOW, the ML60851D is selected
and ready to read or write data.
Read Strobe. When this signal is asserted LOW, the Read instruction is
executed.
Write Strobe. When this signal is asserted LOW, the Write instruction is
executed.
Interrupt Request. When this signal is asserted, the ML60851D makes an
interrupt request to the application.
DMA Request. This signal requests the Endpoint FIFO to make a DMA transfer.
I/O
AD7:AD0
I
A7:A0
LOW
I
CS
LOW
I
RD
LOW
I
WR
LOW
(Note 1)
LOW
(Note 1)
HIGH
(Note 1)
O
INTR
O
DREQ
I
DACK
DMA Acknowledge Signal. This signal, when asserted, enables accessing
FIFOs, without address bus setting.
When ADSEL is HIGH, the address and
CS
on AD7:AD0 is latched at the
trailing edge of this signal. This signal is ignored when ADSEL is LOW.
When ADSEL is LOW, the address is input on A7:A0 and data is input on
D15:D8 and AD7:AD0. When ADSEL is HIGH, the lower bytes (LSB) of
address and data are multiplexed on AD7:AD0.
System Reset. When this signal is asserted LOW, the ML60851D is reset.
When the ML60851D is powered on, this signal must be asserted for 1
m
s or more.
I
ALE
I
ADSEL
I
RESET
LOW
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